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R
Reserved
FBR[1:0]
Fast Blink Rate
These bits define the fast blink rate for the LED output
pins, as shown in
Table 8.3
FBR1 FBR0
0
0
1
1
R
Reserved
SBR[1:0]
Slow Blink Rate
These bits define the slow blink rate for the LED output
pins, as shown in
Table 8.4
SBR1
0
0
1
1
Register: 0xFF05
System Control (SYSCTRL)
Read/Write
7
6
ERO
0
0
ERO
Enable Reset Output
When set, this bit enables the internally generated
watchdog time-out reset to be driven on the external
reset pin. This bit is not affected by a soft reset.
Table
8.3.
Fast LED Blink Rates (40 MHz Internal
Clock)
Fast Blink Rate
0
8 Hz
1
4 Hz
0
2 Hz
1
1 Hz
Table
8.4.
Slow LED Blink Rates (20 MHz Internal
Clock)
SBR0
Slow Blink Rate
0
2 Hz
1
1 Hz
0
0.5 Hz
1
0.25 Hz
3
R
Defaults:
0
0
0
Fast Blink Period
0.0625 s on/0.0625 s off
0.125 s on/0.125 s off
0.25 s on/0.25 s off
0.5 s on/0.5 s off
Slow Blink Period
0.25 s on/0.25 s off
0.5 s on/0.5 s off
1 s on/1 s off
2 s on/2 s off
2
1
0
LVD
SPEN
EIEN
0
0
0
[7:6]
[5:4]
[3:2]
[1:0]
7
8-7
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