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Table A.2
Register Summary by Address (Cont.)
Address
0xFC10
0xFC11
0xFC12
0xFC13
0xFC14
0xFC20/0xFC28
0xFC21/0xFC29
0xFC22/0xFC2A
0xFC23/0xFC2B
0xFC24/0xFC2C
0xFC25/0xFC2D
0xFD00/0xFD02
0xFD00/0xFD02
0xFD00/0xFD02
0xFD01/0xFD03
0xFD01/0xFD03
0xFD01/0xFD03
0xFD04
0xFD05
0xFD06
0xFE00
0xFE01
0xFE02
0xFE03
0xFE04
A-6
Description
DMA Status (DS)
DMA Transfer Length (DTL)
DMA Source/Destination Low (DSDL)
DMA Source/Destination High (DSDH)
DMA Interrupt (DMAI)
Read Data (RDATA0/RDATA1)
Write Data (WDATA0/WDATA1)
Port Control/Status (PCST0/PCST1)
Physical Address (PHAD0/PHAD1)
Live ESI (LESI0/LESI1)
Manual Data Output (MDATA0/MDATA1)
Own Address (ES0, ES1, ES2 = 000)
Clock (ES0, ES1, ES2 = 010)
Data (ES0, ES1, ES2 = 100)
Control Register Writes
Control Register Reads (ES0 = 0)
Status Register Reads (ES0 = 1)
Miscellaneous
UC Control ITF1
UC Control ITF0
Watchdog Timer Control (WDTC)
Watchdog Secondary Chain (WDSC)
Watchdog Final Chain (WDFC)
Miscellaneous Control (MCR)
Interrupt Status (ISR)
Register Summary
R/W
Page #
Read/Write
4-14
Read/Write
4-15
Read/Write
4-16
Read/Write
4-16
Read/Write
4-17
Read/Write
5-3
Read/Write
5-3
Read/Write
5-3
Read Only
5-5
Read Only
5-5
Read/Write
5-6
Read/Write
6-3
Read/Write
6-3
Read/Write
6-4
Write Only
6-5
Read Only
6-6
Read Only
6-8
Read Only
6-9
Read/Write
6-10
Read/Write
6-11
Read/Write
7-3
Read Only
7-5
Read Only
7-5
Read/Write
7-6
Read/Write
7-7
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