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2.3 SCSI Core Operation
2.3.1 Recommended Use of SCSI High ID Pins
Figure 2.2
SYM53C040 Memory Map
0x0000
Interrupt Vectors
0x0032
0x0033
16 Kbytes Internal RAM
0x3FFF
0x4000
47 Kbytes External
Address Space
0xFBFF
0xFC00
1 Kbyte Internal
Features Registers
0xFFFF
The address decode block in the SYM53C040 decodes addresses
generated by the microcontroller and multiplexes memory space
accesses between the different register and memory blocks according to
the memory map.
The SYM53C040 uses a SCSI core based on the SYM53C80 first
generation SCSI architecture. The SYM53C80 architecture supports
8-bit, asynchronous only SCSI data transfers. It supports both SE and
LVD SCSI transfers. The core contains support for parity generation and
checking, initiator and target operation, arbitration, and interrupts to the
microcontroller. The core is controlled by several registers that are
described in
Chapter
The SCSI core in the SYM53C040 is designed for 8-bit SCSI applications
only. However, the SYM53C040 contains some additional logic that
allows the device to have three SCSI high IDs, in addition to 0–7, so that
the SYM53C040 can be given lower priority on a wide SCSI bus.
However, the SYM53C040 cannot perform selection or reselection on a
wide bus; parity checking during the selection/reselection phase may be
SCSI Core Operation
4.
2-5
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