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This notifies the microcontroller to read the WDATAx
(0xFC21/0xFC29) register. The WINT and the RINT bits
are ORed together to generate the port interrupt, which
goes to the microcontroller using the
(ISR)
Note:
The RINT and WINT bits are not self-clearing, so the
microcontroller must clear this bit if the port is interrupt
driven.
Register: 0xFC23/0xFC2B
Physical Address (PHAD0/PHAD1)
Read Only
7
6
PA7
PA6
x
x
PA[7:0]
Physical Address
The Physical Address registers are read only registers
that contain values of the PA inputs.
Register: 0xFC24/0xFC2C
Live ESI (LESI0/LESI1)
Read Only
7
6
PESI/
DWR/
x
x
PESI/
PARALLEL_ESI/ Value
Reading this active low bit gives the state of the PESI/
signal, which is used to select between the SEL_ID and
the bidirectional interface that distinguishes the SFF-8067
interface from SFF-8045.
DWR/
DSK_WR/ Value
Reading this active low bit gives the state of the
DSK_WR/ signal on the SFF-8067 interface. When this
active low bit is cleared, the drive is ready to write data
register.
5
4
3
PA5
PA4
PA3
Default:
x
x
5
4
3
RD/
ACK/
D3
Defaults:
x
x
x
Interrupt Status
2
1
PA2
PA1
x
x
x
2
1
D2
D1
x
x
0
PA0
x
[7:0]
0
D0
x
7
6
5-5
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