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ABSY
Assert BSY/
Writing a 1 into this bit asserts the BSY/ pin onto the
SCSI bus. Conversely, a 0 resets the BSY/ signal.
Asserting BSY/ indicates a successful selection or
reselection, and resetting this bit creates a bus
disconnect condition. Reading this bit reflects the status
of this bit without changing the value.
ASEL
Assert SEL/
Writing a 1 into this bit asserts the SEL/ pin onto the
SCSI bus. SEL/ is normally asserted after arbitration has
been successfully completed. SEL/ may be deasserted
by resetting this bit to a zero. A read of this register bit
simply reflects the status of this bit.
AATN
Assert ATN/
The ATN/ pin may be asserted on the SCSI bus by
setting this bit to a 1 if the Target Mode bit (Mode register
0xFC02, bit 6) is false. ATN/ is normally asserted by the
initiator to request a Message Out bus phase. Note that
since Assert SEL/ and Assert ATN/ are in the same
register, a select with ATN/ may be implemented with one
MPU write. ATN/ may be deasserted by resetting this bit
to a 0. A read of this register bit simply reflects the status
of this bit.
ADB
Assert Data Bus
When set, the Assert Data Bus bit allows the contents of
the
Output Data (ODR)
outputs on the signals DB0/–DB7/. Parity is also
generated and asserted on DBP/. Resetting this bit
disables the output data bus.
When the SYM53C040 is connected as an Initiator, the
outputs are only enabled if the Target Mode bit (Mode
register 0xFC02, bit 6) is false, the received SCSI I/O
signal is false, and the phase signals (C/D, I/O and MSG)
match the contents of the Assert C_D/, Assert I_O/, and
Assert MSG/ in the
(0xFC03).
This bit should also be set during DMA send operations.
register to be enabled as chip
Target Command (TC)
3
2
1
0
register
4-5
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