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4-8
Register: 0xFC03
Target Command (TC)
Read/Write
7
6
LBS
0
0
When connected as a target device, the Target Command register allows
the microcontroller to control the SCSI bus information transfer phase
and/or to assert REQ/ simply by writing this register. The Target Mode
bit (register 0xFC02, bit 6) must be set (1) for bus assertion to occur.
When connected as an initiator with DMA Mode true, if the phase lines
(I_O/, C_D/ and MSG/) do not match the phase bits in this register, a
phase mismatch interrupt is generated when REQ/ goes active. In order
to send data as an initiator, the Assert I_O/, Assert C_D/ and Assert
MSG/ bits must match the corresponding bits in the
Status (CSBS)
register (0xFC04). The Assert REQ/ bit (bit 3) has no
meaning when the SYM53C040 is operating as an initiator.
LBS
Last Byte Sent
In initiator mode, the SCSI core uses this bit to determine
when the last byte of a DMA transfer is sent to the SCSI
bus. This flag is necessary since the End of DMA bit in
the
Bus and Status (BSR)
last byte was received from the DMA function.
R
Reserved
AREQ
Assert REQ/
AMSG
Assert MSG/
ACD
Assert C_D/
AIO
Assert I_O/
These bits, when read together, give the current SCSI
bus phase.
correspond to all possible values of these bits.
SCSI and DMA Registers
4
3
R
AREQ
Defaults:
0
0
0
Table 4.2
describes the SCSI bus phases that
2
1
AMSG
ACD
0
0
Current SCSI Bus
register only reflects when the
0
AIO
0
7
[6:4]
3
2
1
0
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