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5-6
to the SYM53C040. It will be cleared (0) if the PESI/ bit
is cleared (0). If PESI/ is 1, this bit reflects the value of
the PA6 signal.
RD/
DSK_RD/ Value
Reading this active low bit gives the state of the
DSK_RD/ signal on the SFF-8067 interface. When this
active low bit is cleared, the drive is ready to read data
from the SYM53C040. It will be cleared (0) if the PESI/
bit is cleared (0). If PESI/ is 1, this bit reflects the value
of the PA5 signal.
ACK/
ENCL_ACK/ Value
Reading this active low bit gives the state of the
ENCL_ACK/ signal on the SFF-8067 interface. It will be
cleared (0) if the PESI/ bit is cleared (0). If PESI/ is 1, this
bit reflects the value of the PA4 signal.
D[3:0]
8067 Interface Data Nibble Bits
Reading these bits gives the contents of the D[3:0]
signals on the SFF-8067 interface. If PESI/ is 1, these
bits reflect the value of the PA[3:0] signals.
Register: 0xFC25/0xFC2D
Manual Data Output (MDATA0/MDATA1)
Read/Write
7
6
PESI/
DWR/
1
1
The values in these registers are asserted onto the SFF-8067 bus when
the PME bit is set in the PCSTx registers (0xFC22/0xFC2A). These
signals are open drain on the SFF-8067 bus. Therefore, a 1 written to
this register is considered a "soft" value and can be pulled low by another
device on the bus.
PESI/
PARALLEL_ESI/ Value
This active low bit is used to change the state of the
PESI/ signal, which is used to select between the SEL_ID
and the bidirectional interface that distinguishes the
SFF-8067 interface from SFF-8045.
SFF-8067 Registers
5
4
3
RD/
ACK/
D3
Defaults:
1
1
1
[3:0]
2
1
0
D2
D1
D0
1
1
1
5
4
7
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