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7-12
Register: 0xFE0A
Timer 2 Threshold (T2T)
Read/Write
7
6
T2TH7
T2TH6
0
0
T2TH[7:0]
Timer 2 Threshold
These register bits select the time-out threshold for timer 2.
The 8-bit number programmed in this register corresponds
to a multiple of the selected timer resolution, which is
selected by the T2PS bit (0xFE09, bit 4). A value of 0x00
in this register selects the maximum time-out value of 256
times the selected timer resolution.
Register: 0xFE0B
Timer 2 Secondary Chain (T2SC)
Read Only
7
6
R
T2SC6
x
0
R
Reserved
T2SC[6:0]
Timer 2 Secondary Chain
These register bits provide the ability to read the
secondary divide by 100 chain of timer 2. This chain is
enabled with the T2PS bit (0xFE09, bit 4). When enabled,
a value of 100 (decimal) in this register triggers
advancement of the final timer 2 divider chain.
Miscellaneous Registers
5
4
T2TH5
T2TH4
T2TH3
Defaults:
0
0
5
4
T2SC5
T2SC4
T2SC3
Defaults:
0
0
3
2
1
T2TH2
T2TH1
0
0
0
3
2
1
T2SC2
T2SC1
0
0
0
0
T2TH0
0
[7:0]
0
T2SC0
0
7
[6:0]
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