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4-4
Register: 0xFC01
Initiator Command (ICR)
Read/Write
7
6
ARST
AIP
0
0
ARST
Assert SRST
Whenever a 1 is written to this bit, the SRST signal is
asserted on the SCSI bus. The SRST signal will remain
asserted until this bit is reset or until an external chip
reset occurs. After this bit is set, the IRQ output goes
active and all internal logic and control registers are reset
(except for the interrupt latch and the Assert SRST bit).
Writing a 0 to this bit deasserts the SRST signal. Reading
this register bit simply reflects the status of this bit.
AIP
Arbitration In Progress (read only)
This bit is used to determine if arbitration is in progress.
For this bit to be active, the ARB bit (Mode Register
0xFC02, bit 0) must have been set previously. It indicates
that a bus free condition has been detected and that the
chip has asserted BSY/ and the contents of the
Data (ODR)
AIP bit will remain active until the Arbitrate bit is reset.
LA
Lost Arbitration
When active, this read only bit indicates that the SCSI
core has detected a bus free condition, arbitrated for use
of the bus by asserting BSY/ and its ID on the data bus,
and lost arbitration due to SEL/ being asserted by
another bus device. For this bit to be active, the ARB bit
(Mode register 0xFC02, bit 0) must be active.
AACK
Assert ACK/
This bit is used by the bus initiator to assert the ACK/ pin
on the SCSI bus. In order to assert ACK/, the Target
Mode bit (Mode register 0xFC02, bit 6) must be false.
Writing a zero to this bit resets ACK/ on the SCSI bus.
Reading this register bit simply reflects the status of this
bit.
SCSI and DMA Registers
5
4
3
LA
AACK
ABSY
Defaults:
0
0
0
register (0xFC00) onto the SCSI bus. The
2
1
ASEL
AATN
ADB
0
0
Output
0
0
7
6
5
4
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