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Table 3.3
169-Ball BGA List (Alphabetically by Ball Grid Location)
Ball #
Signal
Ball #
A1
NC
C9
A2
RD/
C10
A3
VSS_CORE
C11
A4
RESET/
C12
A5
SCL1
C13
A6
SD1+
D1
A7
SD3+
D2
A8
SD4−
D3
A9
SD6−
D4
A10
VDD_SCSI
D5
A11
SATN−
D6
A12
NC
D7
A13
NC
D8
B1
NC
D9
B2
NC
D10
B3
WR/
D11
B4
VDD_IO
D12
B5
SDA1
D13
B6
SD1−
E1
B7
SD3−
E2
B8
SD5+
E3
B9
SD7+
E4
B10
SDP0−
E5
B11
NC
E6
B12
NC
E7
B13
NC
E8
C1
A10
E9
C2
NC
E10
C3
A8
E11
C4
CLK_SEL
E12
C5
TRST/
E13
C6
SD0−
F1
C7
VDD_SCSI
F2
C8
SD5−
F3
1. NC pins are not connected.
3-6
Signal
Ball #
SD7−
F4
SATN+
F5
RBIAS−
F6
SBSY−
F7
SACK−
F8
A14
F9
A12
F10
A11
F11
VDD_CORE
F12
TESTIN
F13
SD0+
G1
SD2−
G2
SD6+
G3
SDP0+
G4
SBSY+
G5
SACK+
G6
SRST+
G7
SRST−
G8
ALE
G9
PSEN/
G10
A15
G11
A13
G12
A9
G13
VDD_SCSI
H1
SD2+
H2
SD4+
H3
RBIAS+
H4
VDD_SCSI
H5
SMSG−
H6
SSEL+
H7
SSEL−
H8
AD5
H9
AD6
H10
AD7
H11
Signal Descriptions
Signal
Ball #
VDD_IO
H12
AD4
H13
CLK
J1
VSS_IO
J2
SMSG+
J3
SCD+
J4
SCD-
J5
VDD_SCSI
J6
SREQ−
J7
SREQ+
J8
VDD_CORE
AD1
J9
AD2
J10
AD3
J11
AD0
J12
SCL0
J13
VSS_IO
K1
VSS_IO
K2
VSS_IO
K3
SIO+
K4
SIO−
K5
SHID1+
K6
SHID0−
K7
SHID0+
K8
VDD_IO
K9
SDA0
K10
MPLED2_5
MPIO0_0
K11
MPIO0_1
K12
MPIO0_2
K13
MPIO0_6
L1
MPLED0_2
VSS_IO
L2
MPLED0_4
MPIO2_6
L3
MPLED0_6
SHID1−
L4
TDI
L5
DIFFSENS
L6
MPLED1_0
Ball #
Signal
L7
MPLED1_4
SHID2−
L8
SHID2+
L9
MPIO0_3
L10
MPLED2_3
MPIO0_4
L11
MPLED2_6
MPIO0_5
L12
MPLED0_1
L13
MPLED0_7
M1
MPLED1_3
M2
MPIO2_0
M3
M4
MPLED2_7
M5
MPIO3_3
M6
MPLED1_1
TDO
M7
MPLED1_5
TMS
M8
TCK
M9
MPIO0_7
M10 MPLED2_0
MPLED0_0
M11 MPLED2_4
MPLED0_3
M12
MPLED0_5
M13
MPIO1_2
N1
MPIO1_7
N2
MPLED1_7
N3
MPIO2_3
N4
MPLED2_1
N5
N6
MPLED1_2
MPIO3_1
N7
MPLED1_6
MPIO3_2
N8
VSS_CORE
VDD_IO
N9
N10
N11
MPLED2_2
N12
MPIO1_0
N13
MPIO1_4
Signal
MPIO2_2
VDD_IO
NC
MPIO3_0
NC
NC
NC
MPIO1_1
MPIO1_5
MPIO2_1
MPIO2_5
NC
NC
NC
NC
VDD_IO
MPIO1_3
MPIO1_6
MPIO2_4
MPIO2_7
NC
NC
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