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Figure 3.3
SYM53C040 Functional Pin Description
SSEL +
SSEL −
SBSY +
SBSY −
SRST+
SRST −
SREQ+
SREQ −
SACK +
SACK −
SMSG +
SMSG −
SCD +
LVD/SE
SCD −
SCSI
SIO+
Interface
SIO −
SATN+
SATN −
SDP0 +
SDP0 −
SD[7:0] +
SD[7:0] −
DIFFSENS
SHID[2:0] +
SHID[2:0] −
RBIAS +
RBIAS −
3-8
SYM53C040
160-Pin QFP or
169-Ball BGA
Signal Descriptions
MPIO0[7:0]
MPIO1[7:0]
MPIO2[7:0]
MPIO3[3:0]
MPLED0[7:0]
MPLED1[7:0]
MPLED2[7:0]
SCL0
SDA0
SCL1
SDA1
TCK
TMS
TDI
TDO
TRST/
AD[7:0]
A[15:8]
ALE/
PSEN/
WR/
RD/
CLK_SEL
CLK
RESET/
MPIO Pin
Control
MPLED Pin
Control
TWS Interface
(Primary)
TWS Interface
(Secondary)
JTAG
Microcontroller
Interface
Clock
Input
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