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7-6
Register: 0xFE03
Miscellaneous Control (MCR)
Read/Write
7
6
REV3
REV2
REV1
0
0
REV[3:0]
Chip Revision (read only)
These bits define the hardware revision number for the
SYM53C040.
LVD_PWRDWN
LVD Power Down
A value of 1 in this bit powers down the input LVD
transceivers for operation when not in LVD mode.
SISO
SCSI Isolation
When set, this bit 3-states and logically disconnects the
SYM53C040 SCSI port from the SCSI bus when in SE
mode (DIFFSENS = V
TE
TolerANT
This bit is used in LVD mode only. Refer to
information regarding when to set this bit.
ZMODE
High Impedance Mode
Setting this bit to 1 effectively 3-states all output and
bidirectional pads.
Miscellaneous Registers
5
4
REV0
LVD_PWRDWN
Defaults:
0
0
SS
®
Enable
3
2
1
SISO
TE
0
0
0
).
Figure 2.3
0
ZMODE
0
[7:4]
3
2
1
for
0
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