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8-16
Register: 0xFF1B
Multipurpose I/O Bank 2 Latch Mask (MPLM2)
Read/Write
7
6
MPLM2_7 MPLM2_6 MPLM2_5 MPLM2_4 MPLM2_3 MPLM2_2 MPLM2_1 MPLM2_0
1
1
MPLM2_[7:0] Multipurpose I/O Bank 2 Latch Mask
These read/write register bits define the write mask for
the
Multipurpose I/O Bank 2 Latch (MPL2)
(0xFF1C). A value of 1 in any of these bits allows the
corresponding bit in the MPL2 to be modified.
Register: 0xFF1C
Multipurpose I/O Bank 2 Latch (MPL2)
Read/Write
7
6
MPL2_7
MPL2_6
MPL2_5
x
x
MPL2_[7:0]
Multipurpose I/O Bank 2 Latch
These read/write register bits store the power-on value of
the I/O pins MPIO2_0, MPIO2_1, MPIO2_2, MPIO2_3,
MPIO2_4, MPIO2_5, MPIO2_6, and MPIO2_7. The
values on these pins are latched into this register on the
deasserting edge of the RESET/ input signal or the
internal power-on reset.
System Registers
5
4
3
Defaults:
1
1
1
5
4
3
MPL2_4
MPL2_3
Defaults:
x
x
x
2
1
1
1
register
2
1
MPL2_2
MPL2_1
MPL2_0
x
x
0
1
[7:0]
0
x
[7:0]
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