Table of Contents
Advertisement
transferred. This bit is reset when the DMA Mode bit is
reset (0) in the
The SCSI core contains a true End of DMA Status bit
(last byte sent) in bit 7 of the
register.
R
Reserved
PERR
Parity Error
This bit is set if a parity error occurs during a data receive
or a device selection. The Parity Error bit can only be set
(1) if the Enable Parity Check bit (register 0xFC02, bit 5)
is active (1). This bit may be cleared by reading the
Parity/Interrupt (RPI)
IRA
Interrupt Request Active
This bit is set if an enabled interrupt condition occurs. It
can be cleared by reading the
register (0xFC07).
PMATCH
Phase Match
The SCSI signals MSG/, C_D/ and I_O/ represent the
current information transfer phase. The Phase Match bit
indicates whether the current SCSI bus phase matches
the lower three bits of the
Phase Match is continuously updated and is only
significant when the SYM53C040 is operating as a bus
initiator. A phase match is required for data transfers to
occur on the SCSI bus.
BERR
Busy Error
The Busy Error bit is active if an unexpected loss of the
BSY/ signal has occurred. This level sensitive latch is set
whenever the Monitor Busy bit (register 0xFC02, bit 2) is
true and BSY/ is asserted. An unexpected loss of BSY/
will disable any SCSI outputs and will reset the DMA
Mode bit (register 0xFC02, bit 1).
ATN
Attention
This bit reflects the condition of the SCSI bus control
signal ATN/. This signal is normally monitored by a target
device.
Mode (MR)
register (0xFC02).
Target Command (TC)
register (0xFC07).
Reset Parity/Interrupt (RPI)
Target Command (TC)
6
5
Reset
4
3
register.
2
1
4-11
Advertisement
Table of Contents
