Table of Contents
Advertisement
4-16
Register: 0xFC12
DMA Source/Destination Low (DSDL)
Read/Write
7
6
DSDL7
DSDL6
DSDL5
0
0
DSDL[7:0]
DMA Source/Destination Low
These register bits store the least significant byte of the
DMA function's source address for send transfers and
destination address for receive transfers. The read value
of the DSDL and
registers tracks the current source/destination address of
the transfer. If the transfer is interrupted for any reason,
the DSDL and DSDH registers will hold the next address
required, in case the interrupted transfer resumes.
Register: 0xFC13
DMA Source/Destination High (DSDH)
Read/Write
7
6
DSDH7
DSDH6
DSDH5
0
0
DSDH[7:0]
DMA Source/Destination High
These register bits store the most significant byte of the
DMA function's source address for send transfers and
destination address for receive transfers. The read value
of the
registers tracks the current source/destination address of
the transfer. If the transfer is interrupted for any reason,
the DSDL and DSDH registers hold the next address
required, in case the interrupted transfer resumes.
SCSI and DMA Registers
5
4
3
DSDL4
DSDL3
Defaults:
0
0
0
DMA Source/Destination High (DSDH)
5
4
3
DSDH4
DSDH3
Defaults:
0
0
0
DMA Source/Destination Low (DSDL)
2
1
DSDL2
DSDL1
DSDL0
0
0
2
1
DSDH2
DSDH0
DSDH0
0
0
and DSDH
0
0
[7:0]
0
0
[7:0]
Advertisement
Table of Contents
