1. Manuals
  2. Brands
  3. LSI Manuals
  4. Computer Hardware
  5. Symbios SYM53C040
  6. Technical manual

LSI Symbios SYM53C040 Technical Manual

Enclosure services processor
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Symbios
Enclosure Services
Processor
Technical Manual
February 2000
Version 2.5
Order Number S14042
®
SYM53C040
®

Advertisement

Table of Contents
loading

Related Manuals for LSI Symbios SYM53C040

Summary of Contents for LSI Symbios SYM53C040

  • Page 1 ® Symbios SYM53C040 Enclosure Services Processor Technical Manual February 2000 Version 2.5 ® Order Number S14042...
  • Page 2 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.

  • Page 3: Table Of Contents

    Contents Chapter 1 Introduction SYM53C040 Overview SCSI Mode SFF-8067 Mode Features Summary Chapter 2 Functional Description Functional Blocks 2.1.1 SYM53C80-Based SCSI Control Logic 2.1.2 80C32 Microcontroller Core 2.1.3 Two-Wire Serial Interface 2.1.4 SFF-8067 Interface 2.1.5 16 Kbytes SRAM 2.1.6 DMA Function Memory Map SCSI Core Operation 2.3.1...
  • Page 4 2.6.5 Manually Accessing External Two-Wire Serial Devices 2-18 Power-On Configuration Options 2-21 2.7.1 Automatic Branch Generation 2-21 2.7.2 External Serial ROM Configuration 2-22 2.7.3 Serial ROM Chip Address 2-22 2.7.4 Download Port Select 2-23 Resets 2-23 SFF-8067 Mode 2-24 2.10 Interrupts 2-27 2.10.1...
  • Page 5 Chapter 8 System Registers Chapter 9 Electrical Characteristics Operating Requirements 3.3 Volt DC Specifications AC Characteristics 9.3.1 Clock Timing 9.3.2 Reset Signal Microcontroller Interface Timings 9.4.1 External Memory Interface 9.4.2 External Data Read Cycle 9-10 9.4.3 External Data Write Cycle 9-11 Multipurpose Register Access 9-12...
  • Page 6 Programmed I/O Target Transfers 2-10 DMA Target Mode Transfers 2-12 DMA External Memory Access 2-14 Serial Read Operation 2-15 Serial Write Operation 2-15 2.10 Serial ROM Download 2-17 2.11 Two-Wire Serial Slave Data Transmit and Receive 2-19 2.12 Two-Wire Serial Master Data Transmit and Receive 2-20 2.13 SYM53C040 SFF-8067 Interface Control State Diagram...
  • Page 7 Tables Initial ROM Download Contents 2-17 Power-On Configuration Pins and Options 2-21 External Pull-up Values for Automatic Branch Generation 2-22 Serial ROM Chip Addresses 2-23 Register Bits for Interrupt Handling 2-28 Interrupt Handling 2-33 SYM53C040 160-Pin QFP Pin List (Alphabetically by Signal Name) SYM53C040 160-Pin QFP Pin List (Numerically by Pin Number)
  • Page 8 LVD Receiver SCSI Signals—SD[7:0]+, SD[7:0] − , SDP0+, SDP0 − , SREQ/+, SREQ/ − , SACK/+, SACK/ − , SMSG/+, SMSG/ − , SIO/+, SIO/ − , SCD/+, SCD/ − , SATN/+, SATN/ − , SBSY/+, SBSY/ − , SSEL/+, SSEL/ − , SRST/+, SRST/ − , SHID[2:0]+, SHID[2:0] −...
  • Page 9 Preface ® This technical manual provides reference information on the Symbios SYM53C040 Enclosure Services Processor. It contains a complete functional description for the product and includes complete physical and electrical specifications for it. Audience This manual assumes some prior knowledge of current and proposed SCSI, I C, and SFF-8067 standards, including the SAF-TE and SES standards for parallel SCSI devices, as well as a detailed understanding...
  • Page 10 • Chapter 9, Electrical Characteristics, contains the operating conditions and AC timings for the chip and mechanical drawings. • Appendix A, Register Summary Related Publications For background information, please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-199X (SCSI-2) Global Engineering Documents 15 Inverness Way East...
  • Page 11 C Bus Specification For general information about the I C bus, contact Philips Semiconductors at www.semiconductors.philips.com Conventions Used in This Manual The first time a word or phrase is defined in this manual, it is italicized. The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive.
  • Page 12 Preface...

  • Page 13: Chapter 1 Introduction

    This decreases component cost and increases system reliability in distributed storage environments where status information on system resources, such as disk drives, must be available to multiple controllers. SCSI/SAF-TE Enclosure Implementation. Symbios SYM53C040 Enclosure Services Processor Technical Manual...

  • Page 14: Scsi Mode

    1.2 SCSI Mode The SYM53C040 uses the SCSI bus to report system information such as enclosure temperature, power supply status, and disk slot status to the host SCSI controller. It also responds to host SCSI controller commands by generating control outputs to enable and disable disk slots, drive indicator displays, or perform other system tasks.

  • Page 15: Sff-8067 Mode

    1.3 SFF-8067 Mode As an alternative to SCSI, the two SFF-8067 interfaces in the SYM53C040 allow it to communicate data between a Fibre Channel enclosure and the Fibre Channel host, using the SFF-8067 physical interface and the SES protocol to monitor the power supply, cooling system, and other alarms or status indicators in the enclosure.

  • Page 16: Features Summary

    160-pin QFP or 169-ball BGA packaging • Two-wire serial interface for automatic download of external firmware • Full featured SAF-TE firmware provided by LSI Logic • Proven SYM53C80 core for basic SCSI protocol management • 16 mA open drain LED drivers •...

  • Page 17: Chapter 2 Functional Description

    • Section 2.6, “Two-Wire Serial Interface Operation” • Section 2.7, “Power-On Configuration Options” • Section 2.8, “Resets” • Section 2.9, “SFF-8067 Mode” • Section 2.10, “Interrupts” • Section 2.11, “JTAG Boundary Scan Testing” Symbios SYM53C040 Enclosure Services Processor Technical Manual...

  • Page 18: Sym53C040 Block Diagram

    Figure 2.1 SYM53C040 Block Diagram External Firmware Storage and/or Two-Wire Peripheral Devices Two-Wire Two-Wire 80C32 16 K SRAM Serial Serial Microcontroller Interface Interface Microcontroller Address/Data Bus External RAM or ROM (Optional) SYM53C80- Multiplexed Based I/O Register Set Function SCSI Control (Accessible by Logic Firmware Only)

  • Page 19: Functional Blocks

    2.1 Functional Blocks Following are brief descriptions of the main functional blocks comprising the SYM53C040. 2.1.1 SYM53C80-Based SCSI Control Logic The SCSI core in the SYM53C040 is based on the SYM53C80 SCSI controller. The SYM53C80 is a first generation SCSI protocol controller that provides simple, register-based access to SCSI control and data signals.

  • Page 20: Sff-8067 Interface

    2.1.4 SFF-8067 Interface The two SFF-8067 interfaces allow the SYM53C040 to communicate with Fibre Channel SCA-2 devices to transfer SES information to/from Fibre Channel host controllers. The information is transferred across the signal pins used to provide the loop identifier to the SCSI device. Details of the protocol are provided in the SFF-8067 draft specification.

  • Page 21: Scsi Core Operation

    Figure 2.2 SYM53C040 Memory Map 0x0000 Interrupt Vectors 0x0032 0x0033 16 Kbytes Internal RAM 0x3FFF 0x4000 47 Kbytes External Address Space 0xFBFF 0xFC00 1 Kbyte Internal Features Registers 0xFFFF The address decode block in the SYM53C040 decodes addresses generated by the microcontroller and multiplexes memory space accesses between the different register and memory blocks according to the memory map.
  • Page 22 in error and should not be monitored. This limits the SYM53C040 to only target applications, with no disconnects, on a wide bus. To select a high ID for the SYM53C040, connect any of the SCSI high data lines (8–15) to one of the SHID[2:0] pins. The user can monitor the value of the SHID[2:0] pins by reading the SHID[2:0] bits in the Current SCSI Data High (CSDHI)
  • Page 23 Figure 2.3 Initiating Arbitration and Selection/Reselection Write ID Bit to Output Data Register Set Assert SEL/ Bit Reset Assert BSY/ (Reg. 0xFC00) (0xFC01 Bit 2) Bit (0xFC01 Bit 3) Set ARB Check (0xFC02 Bit 0) Selection/ Lost Arb. Bit Reselection (0xFC01 Bit 5) Complete? Set AS_LVD...

  • Page 24: Lvd Link™ Technology

    The LSI Logic LVD Link transceivers operate in LVD and SE modes. The SYM53C040 automatically detects which type of signal is connected, based on voltage detected by the DIFFSENS pin.
  • Page 25 (TC) register are set to the correct state so that a phase match exists. In addition to the phase match condition, the Assert Data Bus bit (bit 0 in register 0xFC01) must be set and the I/O signals must be deasserted for the SCSI core to send data.

  • Page 26: Programmed I/O Target Transfers

    Figure 2.5 Programmed I/O Target Transfers Target Receive Target Send Set Info. Transfer Set Info. Transfer Phase Phase (0xFC03 Bits [2:0] (0xFC03 Bits [2:0] ACK/ Inactive? Set Transfer (0xFC05, Bit 0) Counter in Memory Target Send Only Decrement Write Data to Transfer Counter Output Data Reg.

  • Page 27: Scsi - Dma Transfers

    2.3.4 SCSI - DMA Transfers In the SYM53C040, DMA handshaking with the SCSI core is handled automatically by the DMA function. In order to initiate a DMA transfer to the SCSI core using the DMA function in the SYM53C040, the following sequence must be performed: 1.

  • Page 28: Dma Target Mode Transfers

    Figure 2.6 DMA Target Mode Transfers Write IMR (0xFE0D) to Enable only DMA Interrupts Write Transfer Set Bit 1 in Register Length to DTL 0x87 of the Register (0xFC11) Microprocessor Core to Put It into Power Down Mode Write Source/ Wait for an Interrupt Destination Addresses to 0xFC12, 0xFC13...

  • Page 29: Dma Function

    2.4 DMA Function The SYM53C040 DMA function is designed to automatically handshake with the SCSI core for SCSI send and receive operations. For SCSI send operations, the DMA reads a byte from memory and writes it to the SCSI core when requested. For receive operations, the DMA receives a byte from the SCSI core and writes it to memory.

  • Page 30: Microcontroller Operation

    Figure 2.7 DMA External Memory Access WR/orRD/ AD[7:0] Address Data/Input Address A[15:8] High Address 2.5 Microcontroller Operation The 80C32 microcontroller core used in the SYM53C040 is an 8-bit Intel MCS 51 family compatible device with 256 bytes of internal scratch RAM and no internal ROM.

  • Page 31: Two-Wire Serial Interface Operation

    To enter ONCE mode, hold ALE low while bringing RESET/ to low, then releasing it to high. ONCE mode should be used for testing or diagnostic purposes only, and should be disabled during normal chip operation. 2.6 Two-Wire Serial Interface Operation The Two-Wire Serial interface performs two main functions: it automatically downloads firmware from an external serial EEPROM device, and it serves as a Two-Wire Serial port with full multimaster and...

  • Page 32: Two-Wire Serial Interface Transfer Rate

    2.6.1 Two-Wire Serial Interface Transfer Rate The Two-Wire Serial interface performs all initial downloads at a 78.125 kHz SCL clock rate (with a 40 MHz system clock). At 78.125 kHz, an entire 64 Kbit (8 Kbit x 8) serial EEPROM device can be downloaded in under 945 ms.

  • Page 33: Address And Length Download Configuration

    Figure 2.10 Serial ROM Download Address High Byte Address Low Byte Register 0xFD05 Register 0xFD06 (More data bytes may be 1 0 1 0 a b c Device ID 0 RAH[7:0] RAL[7:0] transferred, EEPROM Chip each followed Master Device ID Addr by an ACK) Slave...

  • Page 34: Firmware Download And Checksum

    2.6.4 Firmware Download and Checksum The first step in the download is to read in the destination address and firmware length. Then the firmware will be read in and written out starting at the destination address. Each byte is bit wise XORed with the previous checksum, starting with zeros.

  • Page 35: Two-Wire Serial Slave Data Transmit And Receive

    Figure 2.11 Two-Wire Serial Slave Data Transmit and Receive Read Byte from Control/Status Register PIN Bit = 0 Read Device Address From Data Register Bit Set? Interrupt Service (0xFC03 Bit 2) Routine Read R/W = 1 R/W = 0 or Write? Slave Transmit Slave Receive (LSB = 1 or 0)

  • Page 36: Two-Wire Serial Master Data Transmit And Receive

    Figure 2.12 Two-Wire Serial Master Data Transmit and Receive Set ES0 Bit In Register 0xFD01 Read Read Write or Write? Read Status Master Transmit (LSB = 1 or Register (0xFD01) Write Data to Data Register (0xFC00) One Byte Left? BB_N = 0? (0xFD01 Bit 0) Read Status Register (0xFD01)

  • Page 37: Power-On Configuration Options

    2.7 Power-On Configuration Options The power-on configuration of the SYM53C040 can be customized for different applications using the AD5, AD[1:0], and A[11:8] pins. Table 2.2 summarizes the functionality that is enabled or disabled by using pull-up resistors on these pins. Table 2.2 Power-On Configuration Pins and Options Signal Name Function...

  • Page 38: External Serial Rom Configuration

    Table 2.3 External Pull-up Values for Automatic Branch Generation External Pull-up on AD1/AD0 First instruction Branch Destination Pull-up/Pull-up 0x8000 Pull-up/None 0x4000 None/Pull-up 0x0033 None/None Fetched from 0x0000 Address locations 0x0033 and 0x0000 correspond to the internal RAM. Address locations 0x8000 and 0x4000 correspond to external memory accesses.

  • Page 39: Download Port Select

    As indicated in the table, the serial ROM chip address mapping is equivalent to the power-on value of signal pins A[10:8]. Table 2.4 Serial ROM Chip Addresses Serial ROM Chip Address AD10 Pull-up AD9 Pull-up AD8 Pull-up 1010 000 None None None 1010 001...

  • Page 40: Sff-8067 Mode

    RESET/ pin is asserted low (0) to reset external devices. The Watchdog Reboot bit is set (0xFE00, bit 7) to indicate that the SYM53C040 has performed a soft reset due to expiration of the watchdog timer. Not all register values in the SYM53C040 are affected by a soft reset. The following bits/registers require a power-on reset to return to their default values: •...
  • Page 41 Interrupts notify the microcontroller of port access. The Read interrupt notifies the microcontroller that the Fibre Channel device is requesting data. The microcontroller responds by clearing the interrupt and writing one byte of data to the RDATA register which will then be transferred to the requesting Fibre Channel device.

  • Page 42: Sym53C040 Sff-8067 Interface Control State Diagram

    Figure 2.13 SYM53C040 SFF-8067 Interface Control State Diagram RESET/ or PESI/ High 8067 Read DSK_RD/ Asserted 8067 IDLE D[3:0] ENCL_ACK/ SEL[6:0] = RDATA[3:0] Deasserted PA[6:0] Discovery PESI/ Asserted DSK_RD/ Deasserted Phase (Low) SEL[3:0] = ENCL_ACK/ ENCL_ACK/ PA[3:0] Asserted Asserted DSK_RD/ Deasserted D[3:0] = ENCL_ACK/ ENCL_ACK/...

  • Page 43: Interrupts

    2.10 Interrupts The SYM53C040 supports the following type of interrupts: • Microcontroller • DMA and SCSI • SFF-8067 • Two-Wire Serial • Masking and Enabling • Polling and Hardware 2.10.1 Microcontroller Interrupts The microcontroller core has two interrupt inputs through which interrupt requests are presented.

  • Page 44: Register Bits For Interrupt Handling

    Table 2.5 Register Bits for Interrupt Handling Register Bit Register or Bit Location Name Function 0xFE04 Interrupt Status Reports to the microcontroller which block asserted the interrupt. Individual bits in this register may be written to force an interrupt on the corresponding bit. Refer to the register description for complete information.

  • Page 45: Dma And Scsi Interrupts

    2.10.1.2 Interrupt Mask Register (0xFE0D) Clearing the bits in this register masks the interrupts corresponding to the bits in the Interrupt Status (ISR) register. 2.10.1.3 Interrupt Destination Register (0xFE0E) This register provides the ability to route an interrupt to either of the two external interrupt inputs of the microcontroller core.
  • Page 46 For send operations, the End of DMA bit is set when the DMA finishes its transfer, but the SCSI transfer may still be in progress. If connected as a target, REQ/ and ACK/ should be sampled until both are false. In the SYM53C040 SCSI core, the Last Byte Sent (bit 7 of the Target Command (TC)

  • Page 47: Sff-8067 Interrupts

    and DBP/ will not be driven even though the Assert Data Bus bit is active. This interrupt is only significant when the SYM53C040 is connected as an initiator. It may be disabled by clearing the DMA Mode bit. Note: It is possible for this interrupt to occur when connected as a target if another device is driving the phase lines to a different state.

  • Page 48: Masking And Enabling Interrupts

    2.10.5 Masking and Enabling Interrupts Table 2.5 lists the registers used for masking and enabling interrupts. For testing purposes, certain types of interrupts can be forced by writing individual bits in the Interrupt Status (ISR) register (0xFE04). These interrupts can be masked by clearing the corresponding bit in the Interrupt Mask (IMR) register (0xFE0D).

  • Page 49: Interrupt Handling

    bits for determining the exact cause of the interrupt. This activity is described in Table 2.6. Table 2.6 Interrupt Handling Location to read to ISR Bit determine cause of Number Interrupt Source interrupt Description SCSI core BSR (0xFC05) Monitors SCSI bus control signals not found in CSBS, plus six other status bits.

  • Page 50: Jtag Boundary Scan Testing

    2.11 JTAG Boundary Scan Testing The SYM53C040 includes support for JTAG boundary scan testing in accordance with the IEEE 1149.1 specification. The device can accept all required boundary scan instructions, as well as the optional CLAMP, HIGH-Z, and IDCODE instructions. The SYM53C040 uses an 8-bit instruction register to support all boundary scan instructions.

  • Page 51: Chapter 3 Signal Descriptions

    A slash (/) at the end of a signal name indicates that the active state occurs when the signal is at a low voltage. When the slash is absent, the signal is active at a high voltage. Symbios SYM53C040 Enclosure Services Processor Technical Manual...

  • Page 52: Sym53C040, 160-Pin Qfp Option

    Figure 3.1 SYM53C040, 160-Pin QFP Option VSS_SCSI VSS_IO SBSY+ SBSY− SACK+ SACK− VDD_SCSI SRST+ SRST− SMSG+ SMSG− PSEN/ VSS_SCSI VDD_IO SSEL+ SSEL− SCD+ SCD− VDD_SCSI SREQ+ SYM53C040 SREQ− SIO+ 160-Pin QFP SIO− Top View VSS_IO VSS_SCSI SCL0 SHID0+ SDA0 SHID0− VDD_IO SHID1+ MPIO0_0...

  • Page 53: Sym53C040 160-Pin Qfp Pin List (Alphabetically By Signal Name)

    Table 3.1 SYM53C040 160-Pin QFP Pin List (Alphabetically by Signal Name) Signal Signal Signal Signal MPIO2_4 SATN− SRST− MPIO2_5 SBSY+ SSEL+ MPIO2_6 SBSY− SSEL− MPIO2_7 SCD+ MPIO3_0 SCD− SCL0 MPIO3_1 MPIO3_2 SCL1 TESTIN MPIO3_3 SD0+ MPLED0_0 SD0− TRST/ MPLED0_1 SD1+ VDD_CORE MPLED0_2 SD1−...

  • Page 54: Sym53C040 160-Pin Qfp Pin List (Numerically By Pin Number)

    Table 3.2 SYM53C040 160-Pin QFP Pin List (Numerically by Pin Number) Signal Signal Signal Signal VSS_IO MPLED0_6 MPLED2_6 RBIAS− MPLED0_7 MPLED2_7 RBIAS+ VDD_IO VSS_IO VSS_SCSI MPIO1_0 MPIO3_0 SATN− MPIO1_1 MPIO3_1 SATN+ MPIO1_2 MPIO3_2 SDP0− MPIO1_3 MPIO3_3 SDP0+ MPIO1_4 VDD_IO VDD_SCSI MPIO1_5 SD7−...

  • Page 55: Sym53C040 169-Ball Bga Top View

    Figure 3.2 SYM53C040 169-Ball BGA Top View SD4 − SD6 − SATN − VSS_CORE RESET/ SCL1 SD1+ SD3+ VDD_SCSI SD1 − SD3 − SDP0 − VDD_IO SDA1 SD5+ SD7+ SD0 − SD5 − SD7 − RBIAS − SBSY − SACK − CLK_SEL TRST/ VDD_SCSI...
  • Page 56 Table 3.3 169-Ball BGA List (Alphabetically by Ball Grid Location) Ball # Signal Ball # Signal Ball # Signal Ball # Signal Ball # Signal MPLED1_4 SD7− VDD_IO SHID2− MPIO2_2 SATN+ SHID2+ VDD_IO VSS_CORE RBIAS− MPIO0_3 MPLED2_3 RESET/ SBSY− VSS_IO MPIO0_4 MPLED2_6 SCL1...
  • Page 57 Table 3.4 169-Ball BGA List (Alphabetically by Signal Name) Signal Ball # Signal Ball # Signal Ball # Signal Ball # Signal Ball # SREQ− MPIO1_6 MPLED2_4 M11 SCD− SREQ+ MPIO1_7 MPLED2_5 K10 SCD+ SRST− MPIO2_0 MPLED2_6 SCL0 SRST+ MPIO2_1 MPLED2_7 SCL1 SSEL−...

  • Page 58: Sym53C040 Functional Pin Description

    Figure 3.3 SYM53C040 Functional Pin Description SSEL + MPIO0[7:0] SSEL − MPIO1[7:0] MPIO Pin SBSY + MPIO2[7:0] Control SBSY − MPIO3[3:0] SRST+ SRST − SREQ+ SREQ − MPLED0[7:0] MPLED Pin SACK + MPLED1[7:0] Control SACK − MPLED2[7:0] SMSG + SMSG − SCD + SYM53C040 LVD/SE...

  • Page 59: Safety Mode Signals

    3.1 Safety Mode Signals The Safety Mode Signals section contains tables describing the signals for the following signal groups: Miscellaneous Signals, SCSI Signals, JTAG Signals Power and Ground Signals. 3.1.1 Miscellaneous Signals Table 3.5 describes the signals for the Miscellaneous Signals group. Table 3.5 Miscellaneous Signals BGA Ball...
  • Page 60 Table 3.5 Miscellaneous Signals (Cont.) BGA Ball Internal Name Number Number Description Pad Type Resistor PSEN/ Active low microcontroller 4 mA, 5 V tolerant None Program Space Enable TTL bidirectional output. Active low microcontroller 4 mA, 5 V tolerant None write output.
  • Page 61 Table 3.5 Miscellaneous Signals (Cont.) BGA Ball Internal Name Number Number Description Pad Type Resistor 25 µA MPIO3_ Multipurpose I/O bank 3 4 mA, 5 V tolerant [3:0] MPIO3_0 = INT0/ to TTL bidirectional pull- microcontroller, if 0xFF05 bit 0 down is set (active low).
  • Page 62 Table 3.5 Miscellaneous Signals (Cont.) BGA Ball Internal Name Number Number Description Pad Type Resistor RESET/ Active low chip reset input. 4 mA open drain None The SYM53C040 has an output, 5 V tolerant internal power-on reset circuit with TTL input which can be relied upon for bidirectional initializing the chip.

  • Page 63: Scsi Signals

    3.1.2 SCSI Signals Table 3.6 describes the signals for the SCSI Signals group. Table 3.6 SCSI Signals BGA Ball Internal Name Number Number Description Pad Type Resistor DIFFSENS SCSI DIFFSENS signal. A low level Analog – input enables SCSI SE mode. A mid- input range level input enables SCSI LVD mode.
  • Page 64 Table 3.6 SCSI Signals (Cont.) BGA Ball Internal Name Number Number Description Pad Type Resistor SIO− SCSI I/O signal. In SE mode, the SE or LVD None SIO+ SIO− pin is the SE signal pin, and the SCSI I/O SIO+ pin should be connected as a virtual ground on the SCSI connector.
  • Page 65 Table 3.6 SCSI Signals (Cont.) BGA Ball Internal Name Number Number Description Pad Type Resistor RBIAS− Bias resistor for LVD operation. See Custom None RBIAS+ Figure 2.4 for a suggested Input implementation. SATN− SCSI ATN signal. In SE mode, the SE or LVD None SATN+...

  • Page 66: Jtag Signals

    3.1.3 JTAG Signals Table 3.7 describes the signals for the JTAG Signals group. Table 3.7 JTAG Signals BGA Ball Internal Name Number Number Description Pad Type Resistor 100 µA Test Clock. The Test Clock pin provides clocking for the JTAG test tolerant pull-up logic and boundary scan.

  • Page 67: Power And Ground Signals

    3.1.4 Power and Ground Signals Table 3.8 describes the signals for the Power and Ground Signals group. Table 3.8 Power and Grounds Signals BGA Ball Internal Name Number Number Description Pad Type Resistor VSS_IO 1, 21, 33, F7, G6, supply for I/O signal pins. Must –...

  • Page 68: Sff-8067 Mode

    3.2 SFF-8067 Mode The SFF-8067 interface is enabled when the DIFFSENS pin is tied to . The SCSI pin functions are reassigned to SFF-8067 port functions as indicated in Table 3.9. Table 3.9 Pin Assignments for SFF-8067 Mode Pin/Ball Signal Name Description 8067 Port Configuration...
  • Page 69 Table 3.9 Pin Assignments for SFF-8067 Mode (Cont.) Pin/Ball Signal Name Description 8067 Port Configuration ENCL_ACK/, 142/E7 When PARALLEL_ESI/ is asserted, Port 0 4 mA open drain SEL_4 this is an active low acknowledge bidirectional signal sourced by the SYM53C040 back to the Fibre Channel device.
  • Page 70 Table 3.9 Pin Assignments for SFF-8067 Mode (Cont.) Pin/Ball Signal Name Description 8067 Port Configuration D1, SEL_1 136/A8 When PARALLEL_ESI/ is asserted, Port 1 4 mA open drain this signal contains bit 1 of a data bidirectional nibble for read and write operations. When PARALLEL_ESI/ is deasserted, this signal is the SEL_1 signal, included for compatibility with...
  • Page 71 Table 3.9 Pin Assignments for SFF-8067 Mode (Cont.) Pin/Ball Signal Name Description 8067 Port Configuration DSK_WR/, 130/B9 When PARALLEL_ESI/ is asserted, Port 1 4 mA open drain SEL_6 this is an active low control signal bidirectional sourced by the drive to the SYM53C040 to indicate the device is ready to write data.
  • Page 72 Table 3.9 Pin Assignments for SFF-8067 Mode (Cont.) Pin/Ball Signal Name Description 8067 Port Configuration 112/F8 This pin contains bit 0 of the Port 1 Input physical address of the enclosure. 111/E11 This pin contains bit 1 of the Port 1 Input physical address of the enclosure.

  • Page 73: Chapter 4 Scsi And Dma Registers

    SYM53C040 register set. Figure 4.1 Register Set Overview 0xFC00 SCSI Core and DMA Registers 0xFC1F 0xFC20 SFF-8067 Registers 0xFCFF 0xFD00 Two-Wire Serial Interface Registers 0xFDFF 0xFE00 Miscellaneous Registers 0xFEFF 0xFF00 System Registers 0xFFFF Symbios SYM53C040 Enclosure Services Processor Technical Manual...
  • Page 74 Table 4.1, the register map, summarizes the SCSI and DMA registers in graphical form. Table 4.1 SCSI and DMA Registers 16 15 Address Current SCSI Data (CSD) (Read) Output Data (ODR) (Write) 0xFC00 Initiator Command (ICR) 0xFC01 Mode (MR) 0xFC02 Target Command (TC) 0xFC03 Current SCSI Bus Status (CSBS)
  • Page 75 Register: 0xFC00 Current SCSI Data (CSD) Read Only DB[7:0] Default: DB[7:0] Current SCSI Data [7:0] The Current SCSI Data register is a read only register that allows the microcontroller to read the active SCSI data bus. Whenever a 1 is read in one of these bits, the corresponding data signal is asserted on the SCSI bus.
  • Page 76 Register: 0xFC01 Initiator Command (ICR) Read/Write ARST AACK ABSY ASEL AATN Defaults: ARST Assert SRST Whenever a 1 is written to this bit, the SRST signal is asserted on the SCSI bus. The SRST signal will remain asserted until this bit is reset or until an external chip reset occurs.
  • Page 77 ABSY Assert BSY/ Writing a 1 into this bit asserts the BSY/ pin onto the SCSI bus. Conversely, a 0 resets the BSY/ signal. Asserting BSY/ indicates a successful selection or reselection, and resetting this bit creates a bus disconnect condition. Reading this bit reflects the status of this bit without changing the value.
  • Page 78 Register: 0xFC02 Mode (MR) Read/Write AS_LVD TGTM Defaults: AS_LVD Arbitration/Selection LVD This bit must be set to perform arbitration, selection, and reselection, and must be cleared upon successful completion of selection or reselection prior to asserting the data bus for any information transfer phases. When set, this bit causes the SCSI data bus to operate in open drain mode, which is a requirement of LVD SCSI as defined in the SPI-2 draft standard.
  • Page 79 Monitor Busy The Monitor Busy bit, when set to a 1, causes an interrupt to be generated for an unexpected loss of BSY/. When the interrupt is generated due to loss of BSY/, the lower 6 bits of the Initiator Command (ICR) register (0xFC01) are reset and all signals are removed from the SCSI bus.
  • Page 80 Register: 0xFC03 Target Command (TC) Read/Write AREQ AMSG Defaults: When connected as a target device, the Target Command register allows the microcontroller to control the SCSI bus information transfer phase and/or to assert REQ/ simply by writing this register. The Target Mode bit (register 0xFC02, bit 6) must be set (1) for bus assertion to occur.
  • Page 81 Table 4.2 SCSI Phase Bit Values Bus Phase Assert MSG/ Assert CD/ Assert IO/ Data Out Undefined Command Message Out Data In Undefined Status Message In Register: 0xFC04 Current SCSI Bus Status (CSBS) Read Only Defaults: The Current SCSI Bus Status register is a read only register that monitors seven SCSI bus control signals plus the data bus parity bit.
  • Page 82 Select Data Bus Parity Register: 0xFC04 Select Enable (SER) Write Only SE[7:0] Defaults: SE[7:0] Selection ID bits [7:0] The Select Enable register is a write only register that is used as a mask to monitor a single ID during a selection attempt.
  • Page 83 transferred. This bit is reset when the DMA Mode bit is reset (0) in the Mode (MR) register (0xFC02). The SCSI core contains a true End of DMA Status bit (last byte sent) in bit 7 of the Target Command (TC) register.
  • Page 84 Acknowledge This bit reflects the condition of the SCSI bus control signal ACK/. This signal is normally monitored by a target device. Register: 0xFC05 DMA Send (DSR) Write Only This register does not have individual bit definitions. Any write to this register will initiate a DMA send, from the DMA core to the SCSI bus, for either initiator or target role operations.
  • Page 85 Register: 0xFC08 Current SCSI Data High (CSDHI) Read Only SHID2 SHID1 SHID0 Defaults: SHID[2:0] Current SCSI Data High [7:5] The Current SCSI Data High register is a read only register that allows the microcontroller to read the active SCSI High ID data bus. This register is used during arbitration to check for higher priority arbitrating devices.
  • Page 86 Register: 0xFC10 DMA Status (DS) Read/Write Defaults: The DMA function in the SYM53C040 provides the capability of transferring up to 256 bytes from memory to the SCSI port or vice versa. The DMA function is designed to handshake automatically with the SCSI core, to offload the microcontroller and increase SCSI throughput.
  • Page 87 normally, or (2) the TIP bit was written to a 0, which manually interrupted the transfer. Transfer in Progress When this bit is written to a 1, the DMA function will begin a transfer. The transfer length is specified in the Transfer Length (DTL) register (0xFC11) and the data source or destination addresses are specified in the...
  • Page 88 Register: 0xFC12 DMA Source/Destination Low (DSDL) Read/Write DSDL7 DSDL6 DSDL5 DSDL4 DSDL3 DSDL2 DSDL1 DSDL0 Defaults: DSDL[7:0] DMA Source/Destination Low [7:0] These register bits store the least significant byte of the DMA function’s source address for send transfers and destination address for receive transfers. The read value of the DSDL and DMA Source/Destination High (DSDH) registers tracks the current source/destination address of...
  • Page 89 Register: 0xFC14 DMA Interrupt (DMAI) Read/Write Defaults: Reserved [7:1] DMA Interrupt This register bit is the interrupt value for the DMA. This interrupt will only be enabled if the IEN bit in the DMA Status register is set. 4-17...

  • Page 90: Scsi And Dma Registers

    4-18 SCSI and DMA Registers...

  • Page 91: Two-Wire Serial Registers

    SYM53C040 register set. Figure 5.1 Register Set Overview 0xFC00 SCSI Core and DMA Registers 0xFC1F 0xFC20 SFF-8067 Registers 0xFCFF 0xFD00 Two-Wire Serial Interface Registers 0xFDFF 0xFE00 Miscellaneous Registers 0xFEFF 0xFF00 System Registers 0xFFFF Symbios SYM53C040 Enclosure Services Processor Technical Manual...

  • Page 92: Sff-8067 Interface Registers

    The SFF-8067 Interface register set allows observation and control of the two SFF-8067 interface ports which are designated as port 0 and port 1. The registers associated with port 0 occupy addresses 0xFC20 through 0xFC27 and the registers associated with port 1 occupy addresses 0xFC28 through 0xFC2F.
  • Page 93 Register: 0xFC20/0xFC28 Read Data (RDATA0/RDATA1) Read/Write Defaults: DB[7:0] 8067 Read Data [7:0] The Read Data bits are read/write bits that contain data to be transferred out on the associated 8067 port in response to a read request at that port. Register: 0xFC21/0xFC29 Write Data (WDATA0/WDATA1) Read/Write...
  • Page 94 associated 8067 port using the MDATA (0xFC25/0xFC2D) register, which contains output data, and the LESI (0xFC24/0xFC2C) register, which is used to read the port pins. Setting this bit disables automatic receive or transmit over the 8067 interface. Reserved (read only) [6:5] Port Busy Flag This bit is set to a 1 when the associated 8067 port is in...
  • Page 95 This notifies the microcontroller to read the WDATAx (0xFC21/0xFC29) register. The WINT and the RINT bits are ORed together to generate the port interrupt, which goes to the microcontroller using the Interrupt Status (ISR) register. Note: The RINT and WINT bits are not self-clearing, so the microcontroller must clear this bit if the port is interrupt driven.
  • Page 96 to the SYM53C040. It will be cleared (0) if the PESI/ bit is cleared (0). If PESI/ is 1, this bit reflects the value of the PA6 signal. DSK_RD/ Value Reading this active low bit gives the state of the DSK_RD/ signal on the SFF-8067 interface.
  • Page 97 DWR/ DSK_WR/ Value When this active low bit is cleared, the drive is ready to write data to the SYM53C040. DSK_RD/ Value When this active low bit is cleared, the drive is ready to read data from the SYM53C040. ACK/ ENCL_ACK/ Value This active low bit is cleared as an acknowledge signal driven by the SYM53C040 in discovery, read, and write...
  • Page 98 SFF-8067 Registers...
  • Page 99 SYM53C040 register set. Figure 6.1 Register Set Overview 0xFC00 SCSI Core and DMA Registers 0xFC1F 0xFC20 SFF-8067 Registers 0xFCFF 0xFD00 Two-Wire Serial Interface Registers 0xFDFF 0xFE00 Miscellaneous Registers 0xFEFF 0xFF00 System Registers 0xFFFF Symbios SYM53C040 Enclosure Services Processor Technical Manual...
  • Page 100 All registers for the Two-Wire Serial interface 0, other than the Control register, are accessed through Register 0xFD00. All registers for the Two-Wire Serial interface 1, other than the Control register, are accessed through Register 0xFD02. To select one of the three registers available at address 0xFD00 or 0xFD02, write the desired value to the ES[0:2] bits in the Control register (0xFD01 or 0xFD03).
  • Page 101 Register: 0xFD00/0xFD02 Own Address (ES0, ES1, ES2 = 000) Read/Write Defaults: Reserved A[6:0] Own Address [6:0] This register contains the address that is used for slave mode operation. If the first byte of transmission matches this bit pattern, then the AAS bit in the Two-Wire Serial interface 0 Control/Status register (0xFD01/0xFD03) will be made active.
  • Page 102 ICF2 ICF1 ICF0 ASF1 ASF0 1024 Examples: 1. A 40 MHz input clock and a maximum 400 kHz SCL output would require D1*D0 to be greater than 100. A best fit would be for D1 to be 32 and D0 to be 4. The value written into the register would be 0x15.
  • Page 103 this register must be read to request a byte from the slave device. This prescribes a dummy read of this register to start data flowing. Each operation will activate the PIN bit located in the Two-Wire Control register [0xFD01/0xFD03 (ES0=1)]. Register: 0xFD01/0xFD03 Control Register Writes Write Only...
  • Page 104 Start When set, this bit signifies that the byte located in the Two-Wire Register 0xFD00/0xFD02 [(ES0, ES1, ES2 = 100] - Data Register) will be sent out on the Two-Wire Serial bus with a start condition as defined in the I specification.
  • Page 105 ES[1:2] Register Selection Bits [5:4] These bits select the Two-Wire Serial register that is read/written by accessing the Two-Wire Serial interface 0 register location. ES2 Description R/W Own Register R/W Clock Register R/W Data Register External Interrupt Enable Setting this bit enables the interrupt output to the microcontroller when the PIN bit (0xFD01/0xFD03, bit 7) is cleared (0).
  • Page 106 Register: 0xFD01/0xFD03 Status Register Reads (ES0 = 1) Read Only RPSS LRB/AD0 BB_N Defaults: Pending Interrupt Not This active low bit is cleared when the Data Register has completed an operation and requires microcontroller intervention to continue operation. RPSS Repeated Start This bit indicates that a repeated start condition occurred on the bus, but only when this interface was involved in the original transfer.
  • Page 107 matches the programmed Own Address (ES0, ES1, ES2 = 000) register (0xFD00/0xFD02) setting. When this bit is cleared, the address matches the general call address. Lost Arbitration Bit In a multiple master environment, if the SYM53C040 loses arbitration to another master on the bus, then it will relinquish control to the other master and set this bit.
  • Page 108 Register: 0xFD05 UC Control ITF1 Read/Write SDAI1 SCLI1 SDAO1 SCLO1 CTL1 Defaults: Reserved [7:5] SDAI1 ITF1 SDA Input This bit indicates the current value on the SDA1 pin. SCLI1 ITF1 SCL Input This bit indicates the current value on the SCL1 pin. SDAO1 ITF1 SDA Output When the CTL1 bit is low, this bit will be the value output...
  • Page 109 Register: 0xFD06 UC Control ITF0 Read/Write SDAI0 SCLI0 SDAO0 SCLO0 CTL0 Defaults: Reserved [7:5] SDAI0 ITF0 SDA Input This bit indicates the current value on the SDA0 pin. SCLI0 ITF0 SCL Input This bit indicates the current value on the SCL0 pin. SDAO0 ITF0 SDA Output When the CTL0 bit is low, this bit will be the value output...

  • Page 110: Two-Wire Serial Registers

    6-12 Two-Wire Serial Registers...

  • Page 111: Register Set Overview

    SYM53C040 register set. Figure 7.1 Register Set Overview 0xFC00 SCSI Core and DMA Registers 0xFC1F 0xFC20 SFF-8067 Registers 0xFCFF 0xFD00 Two-Wire Serial Interface Registers 0xFDFF 0xFE00 Miscellaneous Registers 0xFEFF 0xFF00 System Registers 0xFFFF Symbios SYM53C040 Enclosure Services Processor Technical Manual...

  • Page 112: Miscellaneous Registers

    Table 7.2, the register map, summarizes the Miscellaneous registers in graphical form. Table 7.1 Miscellaneous Registers 16 15 Address Watchdog Timer Control (WDTC) 0xFE00 Watchdog Secondary Chain (WDSC) 0xFE01 Watchdog Final Chain (WDFC) 0xFE02 Miscellaneous Control (MCR) 0xFE03 Interrupt Status (ISR) 0xFE04 Timer 1 Control (T1C) 0xFE05...
  • Page 113 Register: 0xFE00 Watchdog Timer Control (WDTC) Read/Write WDRBT WTHR3 WTHR2 WTHR1 WTHR0 Defaults: The SYM53C040 includes a built-in watchdog timer, which causes a soft reset when it expires. If the watchdog timer expires and forces a chip reset, the reset pad will also assert a low output for resetting other external functions if the Enable Reset Output bit is set (0xFF05, bit 7).

  • Page 114: Possible Watchdog Timer Values (40 Mhz Internal Clock)

    Table 7.3 Possible Watchdog Timer Values (40 MHz Internal Clock) WTHR3 WTHR2 WTHR1 WTHR0 Time-out Value Timer disable 10 ms 20 ms 30 ms 40 ms 50 ms 60 ms 70 ms 80 ms 90 ms 100 ms 110 ms 120 ms 130 ms 140 ms...
  • Page 115 Register: 0xFE01 Watchdog Secondary Chain (WDSC) Read Only WDSC6 WDSC5 WDSC4 WDSC3 WDSC2 WDSC1 WDSC0 Defaults: The values in this register are not affected by a soft reset. Reserved WDSC[6:0] Watchdog Secondary Chain [6:0] These register bits provide the ability to read the 7-bit value in the secondary watchdog timer divider chain.
  • Page 116 Register: 0xFE03 Miscellaneous Control (MCR) Read/Write REV3 REV2 REV1 REV0 LVD_PWRDWN SISO ZMODE Defaults: REV[3:0] Chip Revision (read only) [7:4] These bits define the hardware revision number for the SYM53C040. LVD_PWRDWN LVD Power Down A value of 1 in this bit powers down the input LVD transceivers for operation when not in LVD mode.
  • Page 117 Register: 0xFE04 Interrupt Status (ISR) Read/Write SCSI_INT TW1_INT TW0_INT DMA_INT TMR2_INT TMR1_INT EXS1_INT EXS0_INT Defaults: The individual bits of this register may be written to force an interrupt on the corresponding bit. Clearing these bits does not clear the interrupt, unless it was originally set in this register.
  • Page 118 EXS1_INT 8067 Port 1 Interrupt or MPIO3_1 Interrupt A value of 1 in this bit indicates an interrupt pending from the SFF-8067 port 1 block or an external interrupt received on MPIO3(1). The bit goes to 0 when the interrupt is cleared from MPIO3(1) or cleared from the SFF-8067 port 1 block.
  • Page 119 T1CLR Timer 1 Clear A value of 1 in the T1CLR bit clears the timer. A value of 0 allows the timer to advance beyond the clear state. T1PS Timer 1 Prescaler A value of 1 in the T1PS bit selects the additional divide by 100 secondary divider chain, yielding a timer range of 0.5 ms to 128 ms with a resolution of 0.5 ms per step (with a 40 MHz clock).
  • Page 120 Register: 0xFE07 Timer 1 Secondary Chain (T1SC) Read Only T1SC6 T1SC5 T1SC4 T1SC3 T1SC2 T1SC1 T1SC0 Defaults: Reserved T1SC[6:0] Timer 1 Secondary Chain [6:0] These register bits provide the ability to read the secondary divide by 100 chain of timer 1. This chain is enabled with the T1PS bit (0xFE05, bit 4).
  • Page 121 Register: 0xFE09 Timer 2 Control (T2C) Read/Write T2EXP T2RUN T2CLR T2PS T2IEN Defaults: T2EXP Timer 2 Expired (read only) A value of 1 in the T2EXP bit indicates that the timer has expired and an interrupt has been generated if the T2IEN bit was set when the timer expired.
  • Page 122 Register: 0xFE0A Timer 2 Threshold (T2T) Read/Write T2TH7 T2TH6 T2TH5 T2TH4 T2TH3 T2TH2 T2TH1 T2TH0 Defaults: T2TH[7:0] Timer 2 Threshold [7:0] These register bits select the time-out threshold for timer 2. The 8-bit number programmed in this register corresponds to a multiple of the selected timer resolution, which is selected by the T2PS bit (0xFE09, bit 4).
  • Page 123 Register: 0xFE0C Timer 2 Final Chain (T2FC) Read Only T2FC7 T2FC6 T2FC5 T2FC4 T2FC3 T2FC2 T2FC1 T2FC0 Defaults: T2FC[7:0] Timer 2 Final Chain [7:0] These register bits provide the ability to read the final timer 2 divider chain. The expiration condition for this timer is when the value of this divider chain is equal to the value of the Timer 2 Threshold (T2T)
  • Page 124 IMR5 Two-Wire Interface 0 Interrupt Clearing this bit masks this interrupt. Setting this bit enables the interrupt. IMR4 DMA Interrupt Clearing this bit masks this interrupt. Setting this bit enables the interrupt. IMR3 Timer 2 Interrupt Clearing this bit masks this interrupt. Setting this bit enables the interrupt.
  • Page 125 Register: 0xFE0E Interrupt Destination (IDR) Read/Write IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 Defaults: These register bits provide the ability to route the corresponding interrupts of the Interrupt Status (ISR) register (0xFE04) to either of the two external interrupt inputs of the microcontroller core. A value of 1 written to a bit in this register will route the corresponding interrupt in the ISR register to the external interrupt 1 input of the microcontroller, and a value of 0 written to a given bit will route the corresponding interrupt of...
  • Page 126 7-16 Miscellaneous Registers...

  • Page 127: Register Set Overview

    SYM53C040 register set. Figure 8.1 Register Set Overview 0xFC00 SCSI Core and DMA Registers 0xFC1F 0xFC20 SFF-8067 Registers 0xFCFF 0xFD00 Two-Wire Serial Interface Registers 0xFDFF 0xFE00 Miscellaneous Registers 0xFEFF 0xFF00 System Registers 0xFFFF Symbios SYM53C040 Enclosure Services Processor Technical Manual...

  • Page 128: System Registers

    Table 8.1, the register map, summarizes the System registers in graphical form. Table 8.1 System Registers 16 15 Address Reserved 0xFF00 Power-On Configuration Zero (POC0) 0xFF01 Reserved 0xFF02 Power-On Configuration One (POC1) 0xFF03 LED Blink Rate (LBR) 0xFF04 System Control (SYSCTRL) 0xFF05 Reserved 0xFF06–0xFF07...
  • Page 129 Table 8.1 System Registers (Cont.) Multipurpose LED Bank 0H Input (MLI0H) 0xFF33 Multipurpose LED Bank 0L Latch Mask (MLLM0L) 0xFF34 Multipurpose LED Bank 0H Latch Mask (MLLM0H) 0xFF35 Multipurpose LED Bank 0L Latch (MLL0L) 0xFF36 Multipurpose LED Bank 0H Latch (MLL0H) 0xFF37 Multipurpose LED Bank 1L Output (MLO1L) 0xFF38...
  • Page 130 Register: 0xFF01 Power-On Configuration Zero (POC0) Read Only POC0_7 POC0_6 DLCFG POC0_4 POC0_3 POC0_2 FIBD1 FIBD0 Defaults: POC0_7 Power-On Configuration 7 The reset value of this bit matches the TTL voltage level on the AD7 pin at reset. POC0_6 Power-On Configuration 6 The reset value of this bit matches the TTL voltage level on the AD6 pin at reset.

  • Page 131: Automatic Branch Destination Address

    power-on memory mapping configurations, the SYM53C040 address decode logic will automatically provide the first branch instruction to the microcontroller whenever it fetches from address 0x0000 through 0x0002. The values in bits 0 and 1 define the destination address for this branch instruction, according to Table 8.2.
  • Page 132 POC1_5 Power-On Configuration 1_5 The reset value of this bit matches the TTL voltage level on the A13 pin on reset. POC1_4 Power-On Configuration 1_4 The reset value of this bit matches the TTL voltage level on the A12 pin on reset. If high, the download speed will be increased to an SCL of 1250 kHz.

  • Page 133: Fast Led Blink Rates (40 Mhz Internal Clock)

    Reserved [7:6] FBR[1:0] Fast Blink Rate [5:4] These bits define the fast blink rate for the LED output pins, as shown in Table 8.3. Table 8.3 Fast LED Blink Rates (40 MHz Internal Clock) FBR1 FBR0 Fast Blink Rate Fast Blink Period 8 Hz 0.0625 s on/0.0625 s off 4 Hz...
  • Page 134 Reserved [6:3] SCSI LVD Mode (read only) This read only bit is set when the SCSI interface is in LVD mode. SPEN Serial Port Enable When this bit is set to 1, the MPIO3_2 pin is mapped to the TXD serial port function of the microcontroller core and the MPIO3_3 pin is mapped to the RXD serial port function of the microcontroller core.
  • Page 135 Register: 0xFF09 Multipurpose I/O Bank 0 Enable (MPE0) Read/Write MPE0_7 MPE0_6 MPEO_5 MPEO_4 MPEO_3 MPEO_2 MPEO_1 MPEO_0 Defaults: MPE0_[7:0] Multipurpose I/O Bank 0 Enable [7:0] These bits control the output enables on the I/O pins MPIO0_0, MPIO0_1, MPIO0_2, MPIO0_3, MPIO0_4, MPIO0_5, MPIO0_6, and MPIO0_7.
  • Page 136 Register: 0xFF0B Multipurpose I/O Bank 0 Latch Mask (MPLM0) Read/Write MPLM0_7 MPLM0_6 MPLM0_5 MPLM0_4 MPLM0_3 MPLM0_2 MPLM0_1 MPLM0_0 Defaults: MPLM0_[7:0] Multipurpose I/O Bank 0 Latch Mask [7:0] These read/write register bits define the write mask for Multipurpose I/O Bank 0 Latch (MPL0) register (0xFF0C).
  • Page 137 Register: 0xFF0D Multipurpose I/O Bank 0 Pull-down Enable (MPPE0) Read/Write MPPE0_7 MPPE0_6 MPPE0_5 MPPE0_4 MPPE0_3 MPPE0_2 MPPE0_1 MPPE0_0 Defaults: MPPE0_[7:0] Multipurpose I/O Bank 0 Pull-down Enable [7:0] These read/write register bits determine if pull-downs are active on the I/O pins MPIO0_0, MPIO0_1, MPIO0_2, MPIO0_3, MPIO0_4, MPIO0_5, MPIO0_6, and MPIO0_7.
  • Page 138 Register: 0xFF11 Multipurpose I/O Bank 1 Enable (MPE1) Read/Write MPE1_7 MPE1_6 MPE1_5 MPE1_4 MPE1_3 MPE1_2 MPE1_1 MPE1_0 Defaults: MPE1_[7:0] Multipurpose I/O Bank 1 Enable [7:0] These bits control the output enables on the I/O pins MPIO1_0, MPIO1_1, MPIO1_2, MPIO1_3, MPIO1_4, MPIO1_5, MPIO1_6, and MPIO1_7.
  • Page 139 Register: 0xFF13 Multipurpose I/O Bank 1 Latch Mask (MPLM1) Read/Write MPLM1_7 MPLM1_6 MPLM1_5 MPLM1_4 MPLM1_3 MPLM1_2 MPLM1_1 MPLM1_0 Defaults: MPLM1_[7:0] Multipurpose I/O Bank 1 Latch Mask [7:0] These read/write register bits define the write mask for Multipurpose I/O Bank 1 Latch (MPL1) register (0xFF14).
  • Page 140 Register: 0xFF15 Multipurpose I/O Bank 1 Pull-down Enable (MPPE1) Read/Write MPPE1_7 MPPE1_6 MPPE1_5 MPPE1_4 MPPE1_3 MPPE1_2 MPPE1_1 MPPE1_0 Defaults: MPPE1_[7:0] Multipurpose I/O Bank 1 Pull-down Enable [7:0] These read/write register bits determine if pull-downs are active on the I/O pins MPIO1_0, MPIO1_1, MPIO1_2, MPIO1_3, MPIO1_4, MPIO1_5, MPIO1_6, and MPIO1_7.
  • Page 141 Register: 0xFF19 Multipurpose I/O Bank 2 Enable (MPE2) Read/Write MPE2_7 MPE2_6 MPE2_5 MPE2_4 MPE2_3 MPE2_2 MPE2_1 MPE2_0 Defaults: MPE2_[7:0] Multipurpose I/O Bank 2 Enable [7:0] These bits control the output enables on the I/O pins MPIO2_0, MPIO2_1, MPIO2_2, MPIO2_3, MPIO2_4, MPIO2_5, MPIO2_6, and MPIO2_7.
  • Page 142 Register: 0xFF1B Multipurpose I/O Bank 2 Latch Mask (MPLM2) Read/Write MPLM2_7 MPLM2_6 MPLM2_5 MPLM2_4 MPLM2_3 MPLM2_2 MPLM2_1 MPLM2_0 Defaults: MPLM2_[7:0] Multipurpose I/O Bank 2 Latch Mask [7:0] These read/write register bits define the write mask for Multipurpose I/O Bank 2 Latch (MPL2) register (0xFF1C).
  • Page 143 Register: 0xFF1D Multipurpose I/O Bank 2 Pull-down Enable (MPPE2) Read/Write MPPE2_7 MPPE2_6 MPPE2_5 MPPE2_4 MPPE2_3 MPPE2_2 MPPE2_1 MPPE2_0 Defaults: MPPE2_[7:0] Multipurpose I/O Bank 2 Pull-down Enable [7:0] These read/write register bits determine if pull-downs are active on the I/O pins MPIO2_0, MPIO2_1, MPIO2_2, MPIO2_3, MPIO2_4, MPIO2_5, MPIO2_6, and MPIO2_7.
  • Page 144 Register: 0xFF21 Multipurpose I/O Bank 3 Enable (MPE3) Read/Write MPE3_3 MPE3_2 MPE3_1 MPE3_0 Defaults: Reserved [7:4] MPE3_[3:0] Multipurpose I/O Bank 3 Enable [3:0] These bits control the output enables on the I/O pins MPIO3_0, MPIO3_1, MPIO3_2, and MPIO3_3. A value of 1 turns on the pin driver, and a value of 0 3-states the pin.
  • Page 145 Register: 0xFF22 Multipurpose I/O Bank 3 Input (MPI3) Read Only MPI3_3 MPI3_2 MPI3_1 MPI3_0 Defaults: Reserved [7:4] MPI3_[3:0] Multipurpose I/O Bank 3 Input [3:0] These read only bits read the live input values on the I/O pins MPIO3_0, MPIO3_1, MPIO3_2, and MPIO3_3. Register: 0xFF23 Multipurpose I/O Bank 3 Latch Mask (MPLM3) Read/Write...
  • Page 146 Register: 0xFF24 Multipurpose I/O Bank 3 Latch (MPL3) Read/Write MPL3_3 MPL3_2 MPL3_1 MPL3_0 Defaults: Reserved [7:4] MPL3_[3:0] Multipurpose I/O Bank 3 Latch [3:0] These read/write register bits store the power-on value of the I/O pins MPIO3_0, MPIO3_1, MPIO3_2, and MPIO3_3. The values on these pins are latched into this register on the deasserting edge of the RESET/ input signal or the internal power-on reset.

  • Page 147: Led Behavior

    Register: 0xFF30 Multipurpose LED Bank 0L Output (MLO0L) Read/Write MLO0_3A MLO0_3B MLO0_2A MLO0_2B MLO0_1A MLO0_1B MLO0_0A MLO0_0B Defaults: MLO0_[3A:0A], [3B:0B] Multipurpose LED Bank 0L Output [7:0] The bits in this register control the Multipurpose LED Bank 0 pins MPLED0_3, MPLED0_2, MPLED0_1, and MPLED0_0.
  • Page 148 Register: 0xFF31 Multipurpose LED Bank 0H Output (MLO0H) Read/Write MLO0_7A MLO0_7B MLO0_6A MLO0_6B MLO0_5A MLO0_5B MLO0_4A MLO0_4B Defaults: MLO0_[7A:4A], [7B:4B] Multipurpose LED Bank 0H Output [7:0] The bits in this register control the Multipurpose LED Bank 0 pins MPLED0_7, MPLED0_6, MPLED0_5, and MPLED0_4.
  • Page 149 Register: 0xFF33 Multipurpose LED Bank 0H Input (MLI0H) Read Only MLL0_7 MLL0_6 MLL0_5 MLL0_4 Defaults: Reserved [7, 5, 3, 1] MLL0_[7:4] Multipurpose LED Bank 0H Input [6, 4, 2, 0] The bits in this read only register read the live input value on the MPLED0_4, MPLED0_5, MPLED0_6, and MPLED0_7 pins.
  • Page 150 Register: 0xFF35 Multipurpose LED Bank 0H Latch Mask (MLLM0H) Read/Write MLLM0_7 MLLM0_6 MLLM0_5 MLLM0_4 Default: Reserved [7, 5, 3, 1] MLLM0_[7:4] Multipurpose LED Bank 0H Latch Mask [6, 4, 2, 0] The bits in this read/write register define the write mask for the Multipurpose LED Bank 0L Latch (MLL0L) register...

  • Page 151: Led Bank 1 Behavior

    Register: 0xFF37 Multipurpose LED Bank 0H Latch (MLL0H) Read/Write MLL0_7 MLL0_6 MLL0_5 MLL0_4 Defaults: Reserved [7, 5, 3, 1] MLL0_[7:4] Multipurpose LED Bank 0H Latch [6, 4, 2, 0] The bits in this read/write register store the power-on value of the I/O pins MPLED0_4, MPLED0_5, MPLED0_6, and MPLED0_7.
  • Page 152 The slow blink and fast blink rates are defined in the Blink Rate (LBR) register (0xFF04). All LED pins have 16 mA open drain drivers. Turning the LED off (MLOx_xA = 0 and MLOx_xB = 0) effectively 3-states the driver. Register: 0xFF39 Multipurpose LED Bank 1H Output (MLO1H) Read/Write...
  • Page 153 Multipurpose LED Bank 2 Output registers (0xFF38, 0xFF39), they can be used as input pins. Register: 0xFF3B Multipurpose LED Bank 1H Input (MLI1H) Read Only MLI1_7 MLI1_6 MLI1_5 MLI1_4 Defaults: Reserved [7, 5, 3, 1] MLI1_[7:4] Multipurpose LED Bank 1H Input [6, 4, 2, 0] The bits in this read only register read the live input value on the MPLED1_4, MPLED1_5, MPLED1_6, and...
  • Page 154 Register: 0xFF3D Multipurpose LED Bank 1H Latch Mask (MLLM1H) Read/Write MLLM1_7 MLLM1_6 MLLM1_5 MLLM1_4 Defaults: Reserved [7, 5, 3, 1] MLLM1_[7:4] Multipurpose LED Bank 1H Latch Mask [6, 4, 2, 0] These read/write register bits define the write mask for Multipurpose LED Bank 1L Latch (MLL1L) register (0xFF3E) and the...

  • Page 155: Led Bank 2 Behavior

    Register: 0xFF3F Multipurpose LED Bank 1H Latch (MLL1H) Read/Write MLL1_7 MLL1_6 MLL1_5 MLL1_4 Defaults: Reserved [7, 5, 3, 1] MLL1_[7:4] Multipurpose LED Bank 1H Latch [6, 4, 2, 0] The bits in these read/write registers store the power-on value of the I/O pins MPLED1_4, MPLED1_6, MPLED1_5, and MPLED1_7.
  • Page 156 The slow blink and fast blink rates are defined in the Blink Rate (LBR) register (0xFF04). All LED pins have 16 mA open drain drivers. Turning the LED off (MLOx_xA = 0 and MLOx_xB = 0) effectively 3-states the driver. Register: 0xFF41 Multipurpose LED Bank 2H Output (MLO2H) Read/Write...
  • Page 157 Multipurpose LED Bank 2 Output Registers (0xFF38, 0xFF39), they can be used as input pins. Register: 0xFF43 Multipurpose LED Bank 2H Input (MLI2H) Read Only MLI2_7 MLI2_6 MLI2_5 MLI2_4 Default: Reserved [7, 5, 3, 1] MLI2_[7:4] Multipurpose LED Bank 2H Input [6, 4, 2, 0] The bits in this read only register read the live input value on the MPLED2_4, MPLED2_5, MPLED2_6, and...
  • Page 158 Register: 0xFF45 Multipurpose LED Bank 2H Latch Mask (MLLM2H) Read/Write MLLM2_7 MLLM2_6 MLLM2_5 MLLM2_4 Defaults: Reserved [7, 5, 3, 1] MLLM2_[7:4] Multipurpose LED Bank 2H Latch Mask [6, 4, 2, 0] The bits in this read/write register define the write mask for the Multipurpose LED Bank 2L Latch (MLL2L) register...
  • Page 159 Register: 0xFF47 Multipurpose LED Bank 2H Latch (MLL2H) Read/Write MLL2_7 MLL2_6 MLL2_5 MLL2_4 Defaults: Reserved [7, 5, 3, 1] MLL2_[7:4] Multipurpose LED Bank 2H Latch [6, 4, 2, 0] These read/write register bits store the power-on value of the I/O pins MPLED2_4, MPLED2_6, and MPLED2_7. The values on these pins are latched into this register on the deasserting edge of the RESET/ input signal or the internal power-on reset.
  • Page 160 8-34 System Registers...

  • Page 161: Chapter 9 Electrical Characteristics

    Section 9.4, “Microcontroller Interface Timings” • Section 9.5, “Multipurpose Register Access” • Section 9.6, “Two-Wire Serial Timings” • Section 9.7, “SFF-8067 Interface Timings” • Section 9.8, “SCSI Timings” • Section 9.9, “Mechanical Drawings” Symbios SYM53C040 Enclosure Services Processor Technical Manual...

  • Page 162: Operating Requirements

    9.1 Operating Requirements Table 9.1 Absolute Maximum Stress Ratings Symbol Parameter Units Test Conditions −55 ° Storage temperature – −0.5 Supply voltage – Vss −0.3 Input voltage +0.3 – Latch-up current ±150 – – Electrostatic discharge – Mil-STD 883C, Method 3015.7 1.

  • Page 163: Volt Dc Specifications

    9.2 3.3 Volt DC Specifications , SDP0+, SDP0 − , SREQ+, − Table 9.3 LVD Driver SCSI Signals—SD[7:0]+ SD[7:0] SREQ − , SACK/+, SACK/ − , SHID[2:0]+, SHID[2:0] − , SMSG/+, SMSG/ − , SIO/+, SIO/ − , SCD/+, SCD/ − , SATN/+, SATN/ − , SBSY/+, SBSY/ − , SSEL/+, SSEL/ − , SRST/+, SRST/ −...

  • Page 164: Lvd Receiver

    LVD Receiver SCSI Signals—SD[7:0]+, SD[7:0] − , SDP0+, SDP0 − , SREQ/+, Table 9.4 SREQ/ − , SACK/+, SACK/ − , SMSG/+, SMSG/ − , SIO/+, SIO/ − , SCD/+, SCD/ − , SATN/+, SATN/ − , SBSY/+, SBSY/ − , SSEL/+, SSEL/ − , SRST/+, SRST/ − , SHID[2:0]+, SHID[2:0] −...

  • Page 165: Scsi Signals—Diffsens

    Table 9.6 SCSI Signals—DIFFSENS Symbol Parameter Units Test Conditions High differential sense voltage – (indicates SFF-8067 mode) Vss −0.3 Low differential sense voltage – (indicates SE SCSI operation) Mid-level differential sense voltage – (indicates LVD mode) −10 µA 3-state leakage –...

  • Page 166: Bidirectional Signals—Reset/, Testout, Cl0, Sda0 Scl1, Sda1

    Table 9.9 Bidirectional Signals—RESET/, TESTOUT, CL0, SDA0, SCL1, SDA1 Symbol Parameter Units Test Conditions Input high voltage – Input low voltage – Vss –0.5 −4 mA Output high voltage Output low voltage 4 mA −10 µA Pull-up current – Table 9.10 Bidirectional Signals—MPIO0[7:0], MPIO1[7:0], MPIO2[7:0], MPIO3[3:0] Symbol Parameter...

  • Page 167: Ac Characteristics

    9.3 AC Characteristics 9.3.1 Clock Timing Figure 9.3 SYM53C040 Clock Waveforms CLK/SCLK Table 9.12 SYM53C040 Clock Timings Symbol Parameter Units CLK clock period CLK low time – CLK high time – CLK slew rate – V/ns 1. Duty cycle not to exceed 60/40. AC Characteristics...

  • Page 168: Reset Signal

    9.3.2 Reset Signal Figure 9.4 Reset Waveforms RESET/ Table 9.13 Reset Timings Symbol Parameter Units Reset Input Pulse Width 10 tclk – Reset Output Pulse Width 15 tclk – Reset deasserted setup to CLK high – Electrical Characteristics...

  • Page 169: Microcontroller Interface Timings

    9.4 Microcontroller Interface Timings This section provides timing information for the microcontroller interface. The AC characteristics described in this section apply over the entire range of operating conditions for the SYM53C040. 9.4.1 External Memory Interface Figure 9.5 External Memory Interface Waveforms PSEN/ ADDR INSTR...

  • Page 170: External Data Read Cycle

    9.4.2 External Data Read Cycle Figure 9.6 External Data Read Waveforms PSEN/ AD[7:0] ADDR DATA IN A[7:0] ADDR ADDR A[15:8] ADDR ADDR ADDR Table 9.15 External Data Read Timings Symbol Parameter Units ALE to RD/ = Minimum delay from ALE falling to RD/ falling –...

  • Page 171: External Data Write Cycle

    9.4.3 External Data Write Cycle Figure 9.7 External Data Write Waveforms PSEN/ AD[7:0] ADDR DATA A[7:0] ADDR ADDR A[15:8] ADDR ADDR ADDR Table 9.16 External Data Write Timings Symbol Parameter Units ALE to WR/ = Minimum delay from ALE falling to WR/ –...

  • Page 172: Multipurpose Register Access

    9.5 Multipurpose Register Access The timings in Table 9.17 apply to register accesses to control the MPIO and MPLED pins. Please refer to Chapter 2 for more information on specifying the operation of these pins. Table 9.17 Multipurpose I/O and LED Timings Parameter Units Shared input setup...

  • Page 173: Two-Wire Serial Timings

    9.6 Two-Wire Serial Timings The SYM53C040 Two-Wire Serial interface timings comply with the I specification. Please refer to the specification for more information. Figure 9.8 Two-Wire Serial Bus Timings Start Address, Data Data Allowed Stop Start Condition or Acknowledge to Change Condition Condition Valid...

  • Page 174: Sff-8067 Interface Timings

    9.7 SFF-8067 Interface Timings Figure 9.9 SFF-8067 Discovery Phase Waveforms PESI/ Driven By Drive DSK_RD/ Driven By Drive DSK_WR/ Driven By Drive ENCL_ACL Driven By SYM53C040 D[3:0] SEL[3:0] SEL[3:0]/ Driven By SYM53C040 Figure 9.10 SFF-8067 Write Phase Waveforms PESI/ Logic 0 Driven By Drive DSK_RD/ Logic 1...

  • Page 175: Sff-8067 Read Waveforms

    Figure 9.11 SFF-8067 Read Waveforms PESI/ Driven By Drive DSK_RD/ Driven By Drive DSK_WR/ Driven By Drive ENCL_ACL Driven By SYM53C040 D[3:0] High Nibble Low Nibble Driven By SYM53C040 Table 9.20 SFF-8067 Interface Timings Parameter Description Units PESI/ LOW to ENCL_ACK/ LOW –...

  • Page 176: Scsi Timings

    9.8 SCSI Timings 9.8.1 Initiator Asynchronous Send Figure 9.12 Initiator Asynchronous Send Waveforms n + 1 SREQ/ n + 1 SACK/ SD[15:0], Valid n + 1 Valid n SDP1/, SDP0/ Table 9.21 Initiator Asynchronous Send Timings Symbol Description Units SACK asserted from SREQ deasserted –...

  • Page 177: Initiator Asynchronous Receive

    9.8.2 Initiator Asynchronous Receive Figure 9.13 Initiator Asynchronous Receive Waveforms n + 1 SREQ/ n + 1 SACK/ SD[15:0], Valid n + 1 Valid n SDP1/, SDP0/ Table 9.22 Initiator Asynchronous Receive Timings Symbol Description Units – ACK asserted from REQ deasserted –...

  • Page 178: Target Asynchronous Send

    9.8.3 Target Asynchronous Send Figure 9.14 Target Asynchronous Send Waveforms n + 1 SREQ/ n + 1 SACK/ SD[15:0], Valid n + 1 Valid n SDP1/, SDP0/ Table 9.23 Target Asynchronous Send Timings Symbol Description Units – REQ deasserted from REACKQ asserted –...

  • Page 179: Target Asynchronous Receive

    9.8.4 Target Asynchronous Receive Figure 9.15 Target Asynchronous Receive Waveforms n + 1 SREQ/ n + 1 SACK/ SD[15:0], Valid n + 1 Valid n SDP1/, SDP0/ Table 9.24 Target Asynchronous Receive Timings Symbol Description Units REQ deasserted from ACK asserted –...
  • Page 180 9.9 Mechanical Drawings For printed circuit board land patterns that accept LSI Logic components, it is recommended that customers refer to the IPC standards (Institute for Interconnecting and Packaging Electronic Circuits). Specification IPC-SM-782, Surface Mount Design and Land Pattern Standard is an established method of designing land patterns.

  • Page 181: Mechanical Drawings

    Figure 9.16 160 LD-Pin PQFP (PZ) Mechanical Drawing (Sheet 1 of 2) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code PZ. Mechanical Drawings...
  • Page 182 Figure 9.16 160 LD-pin PQFP (PZ) Mechanical Drawing (Sheet 2 of 2) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code PZ. 9-22...

  • Page 183: Pin Pbga (Gv) Mechanical Drawing

    Figure 9.17 169-Pin PBGA (GV) Mechanical Drawing Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code GV. Mechanical Drawings...
  • Page 184 9-24 Electrical Characteristics...

  • Page 185: Appendix A Register Summary

    DMA Transfer Length (DTL) 0xFC11 Read/Write 4-15 Initiator Command (ICR) 0xFC01 Read/Write Interrupt Destination (IDR) 0xFE0E Read/Write 7-15 Interrupt Mask (IMR) 0xFE0D Read/Write 7-13 Interrupt Status (ISR) 0xFE04 Read/Write LED Blink Rate (LBR) 0xFF04 Read/Write Symbios SYM53C040 Enclosure Services Processor Technical Manual...
  • Page 186 Table A.1 Register Summary by Description (Cont.) Description Address Page # Live ESI (LESI0/LESI1) 0xFC24/0xFC2C Read Only Manual Data Output (MDATA0/MDATA1) 0xFC25/0xFC2D Read/Write Miscellaneous 0xFD04 Read Only Miscellaneous Control (MCR) 0xFE03 Read/Write Mode (MR) 0xFC02 Read/Write Multipurpose I/O Bank 0 Enable (MPE0) 0xFF09 Read/Write Multipurpose I/O Bank 0 Input (MPI0)
  • Page 187 Table A.1 Register Summary by Description (Cont.) Description Address Page # Multipurpose I/O Bank 3 Latch (MPL3) 0xFF24 Read/Write 8-20 Multipurpose I/O Bank 3 Latch Mask (MPLM3) 0xFF23 Read/Write 8-19 Multipurpose I/O Bank 3 Output (MPO3) 0xFF20 Read/Write 8-17 Multipurpose I/O Bank 3 Pull-down Enable (MPPE3) 0xFF25 Read/Write 8-20...
  • Page 188 Table A.1 Register Summary by Description (Cont.) Description Address Page # Multipurpose LED Bank 2L Latch (MLL2L) 0xFF46 Read/Write 8-32 Multipurpose LED Bank 2L Latch Mask (MLLM2L) 0xFF44 Read/Write 8-31 Multipurpose LED Bank 2L Output (MLO2L) 0xFF40 Read/Write 8-29 Output Data (ODR) 0xFC00 Write Only Own Address (ES0, ES1, ES2 = 000)

  • Page 189: A.2 Register Summary By Address

    Table A.1 Register Summary by Description (Cont.) Description Address Page # Timer 2 Threshold (T2T) 0xFE0A Read/Write 7-12 UC Control ITF0 0xFD06 Read/Write 6-11 UC Control ITF1 0xFD05 Read/Write 6-10 Watchdog Final Chain (WDFC) 0xFE02 Read Only Watchdog Secondary Chain (WDSC) 0xFE01 Read Only Watchdog Timer Control (WDTC)
  • Page 190 Table A.2 Register Summary by Address (Cont.) Address Description Page # 0xFC10 DMA Status (DS) Read/Write 4-14 0xFC11 DMA Transfer Length (DTL) Read/Write 4-15 0xFC12 DMA Source/Destination Low (DSDL) Read/Write 4-16 0xFC13 DMA Source/Destination High (DSDH) Read/Write 4-16 0xFC14 DMA Interrupt (DMAI) Read/Write 4-17 0xFC20/0xFC28...
  • Page 191 Table A.2 Register Summary by Address (Cont.) Address Description Page # 0xFE05 Timer 1 Control (T1C) Read/Write 0xFE06 Timer 1 Threshold (T1TH) Read/Write 0xFE07 Timer 1 Secondary Chain (T1SC) Read Only 7-10 0xFE08 Timer 1 Final Chain (T1FC) Read Only 7-10 0xFE09 Timer 2 Control (T2C)
  • Page 192 Table A.2 Register Summary by Address (Cont.) Address Description Page # 0xFF15 Multipurpose I/O Bank 1 Pull-down Enable (MPPE1) Read/Write 8-14 0xFF18 Multipurpose I/O Bank 2 Output (MPO2) Read/Write 8-14 0xFF19 Multipurpose I/O Bank 2 Enable (MPE2) Read/Write 8-15 0xFF1A Multipurpose I/O Bank 2 Input (MPI2) Read Only 8-15...
  • Page 193 Table A.2 Register Summary by Address (Cont.) Address Description Page # 0xFF3C Multipurpose LED Bank 1L Latch Mask (MLLM1L) Read/Write 8-27 0xFF3D Multipurpose LED Bank 1H Latch Mask (MLLM1H) Read/Write 8-28 0xFF3E Multipurpose LED Bank 1L Latch (MLL1L) Read/Write 8-28 0xFF3F Multipurpose LED Bank 1H Latch (MLL1H) Read/Write...
  • Page 194 A-10 Register Summary...

  • Page 195: Index

    4-10 AIO assert I_O/ bit bus busy bit AIO bit bus error detection bit AIP bit busy bit AMSG assert MSG/ bit busy error bit 4-11 AMSG bit ARB bit Symbios SYM53C040 Enclosure Services Processor Technical Manual IX-1...
  • Page 196 DMA transfer length 2-11 DMA transfer length register 4-15 C_D bit DMA transfers 2-11 checksum error bit DMA_INT bit chip revision bits DMAI register 4-17 CKSUM bit download configuration select bit clock register download ROM address bits command/data bit download serial ROM bit configuration ROM download 2-16 DS register...
  • Page 197 ITF0 control bit 6-11 ITF0 SCL input bit 6-11 I/O direction bit 4-14 ITF0 SCL output bit 6-11 I_O bit ITF0 SDA input bit 6-11 I2C bus 2-15 ITF0 SDA output bit 6-11 ICF bit ITF1 control bit 6-10 ITF1 SCL input bit 6-10 idle mode 2-11...
  • Page 198 MLI1L register 8-26 multipurpose I/O bank 0 MLI2H register 8-31 enable register MLI2L register 8-30 input register MLL0H register 8-25 latch mask register 8-10 MLL0L register 8-24 latch register 8-10 MLL1H register 8-29 output register MLL1L register 8-28 pull-down enable register 8-11 MLL2H register 8-33...
  • Page 199 multipurpose LED bank 2L read data register input register 8-30 read interrupt bit latch mask register 8-31 read register full bit latch register 8-32 receive operations 2-13 output register 8-29 register bits 8067 interface data nibble 8067 port 0 interrupt 7-14 7-15 8067 port 1 interrupt...
  • Page 200 busy fast blink rate busy error 4-11 FBR[1:0] FIBD[1:0] checksum error first instruction branch destination chip revision high impedance mode CKSUM I/O direction 4-14 command/data CTL0 6-11 CTL1 6-10 IDR[7:0] 7-15 current SCSI data bus 4-14 current SCSI data high 4-13 IMR[7:0] 7-13...
  • Page 201 MLLM2_[3:0] bits 8-31 latch 8-16 MLLM2_[7:4] 8-32 latch mask 8-16 MLO0_[3A:0A], [3B:0B] 8-21 output 8-14 MLO0_[7A:4A], [7B:4B] 8-22 pull-down enable 8-17 MLO1_[3A:0A], [3B:0B] 8-25 multipurpose I/O bank 3 MLO1_[7A:4A], [7B:4B] 8-26 enable 8-18 MLO2_[3A:0A], [3B:0B] 8-29 input 8-19 MLO2_[7A:4A], [7B:4B] 8-30 latch 8-20...
  • Page 202 T1IEN POC0_[7:6], [4:2] T1PS POC1_[6:4] T1RUN port busy flag T1SC[6:0] 7-10 port manual enable T1TH[7:0] power-on configuration 1_[6:4] T2CLR 7-11 power-on configuration[7:6], [4:2] T2EXP 7-11 T2FC[7:0] 7-13 read interrupt T2IEN 7-11 read register full T2PS 7-11 register selection T2RUN 7-11 repeated start T2SC[6:0] 7-12...
  • Page 203 WDRBT MLLM1H 8-28 WDSC[6:0] MLLM1L 8-27 WINT MLLM2H 8-32 MLLM2L 8-31 write interrupt MLO0H 8-22 write register full MLO0L 8-21 WTHR[3:0] MLO1H 8-26 ZMODE MLO1L 8-25 register selection bits MLO2H 8-30 registers MLO2L 8-29 bus and status 4-10 mode register clock MPE0 control reads...
  • Page 204 latch mask 8-16 start DMA initiator receive 4-12 output 8-14 start DMA target receive 4-12 pull-down enable 8-17 status register reads multipurpose I/O bank 3 summary enable 8-18 by address input 8-19 by description latch 8-20 SYSCTRL latch mask 8-19 system control output 8-17...
  • Page 205 SFF-8067 interface 2-23 2-24 control 2-25 SAF-TE typical implementation interrupts 2-31 SBR[1:0] bits pin assignments 3-18 SCLI0 bit 6-11 typical implementation SCLI1 bit 6-10 SFF-8067 mode 2-24 2-26 SCLO0 bit 6-11 SHID[2:0] bits 4-13 SCLO1 bit 6-10 single-ended mode SCSI arbitration SISO bit SCSI core slave mode stop bit...
  • Page 206 target mode bit overview TC bit 4-14 power-on configuration options 2-21 TE bit selecting a two-wire port 2-23 TGTM bit timings 9-13 timer 1 transfer rate 2-16 clear bit control register expired bit UC control ITF0 register 6-11 final chain register 7-10 UC control ITF1 register 6-10...

  • Page 207: Customer Feedback

    Please include your name, phone number, fax number, and company address so that we may contact you directly for clarification or additional information. Thank you for your help in improving the quality of our documents. Symbios SYM53C040 Enclosure Services Processor Technical Manual...
  • Page 208 Reader’s Comments Fax your comments to: LSI Logic Corporation Technical Publications M/S E-198 Fax: 408.433.4333 ® Please tell us how you rate this document: Symbios SYM53C040 Enclosure Services Processor Technical Manual. Place a check mark in the appropriate blank for each category.
  • Page 209 U.S. Distributors by State A. E. Avnet Electronics Colorado Indiana Minnesota http://www.hh.avnet.com Denver Fort Wayne Champlin B. M. Bell Microproducts, A. E. Tel: 303.790.1662 I. E. Tel: 219.436.4250 B. M. Tel: 800.557.2566 Inc. (for HAB’s) B. M. Tel: 303.846.3065 W. E. Tel: 888.358.9953 Eden Prairie http://www.bellmicro.com...
  • Page 210 U.S. Distributors by State (Continued) New York South Carolina Wisconsin Hauppauge A. E. Tel: 919.872.0712 Milwaukee I. E. Tel: 516.761.0960 W. E. Tel: 919.469.1502 A. E. Tel: 414.513.1500 Long Island W. E. Tel: 800.867.9953 South Dakota A. E. Tel: 516.434.7400 Wauwatosa A.
  • Page 211 Direct Sales Representatives by State (Component and HAB) E. A. Earle Associates Texas E. L. Electrodyne - UT Austin Group 2000 Tel: 512.794.9006 I. S. Infinity Sales, Inc. Arlington ION Associates, Inc. Tel: 817.695.8000 R. A. Rathsburg Associ- Houston ates, Inc. Tel: 281.376.2000 Synergy Associates, Utah...
  • Page 212 Resource Centers LSI Logic Corporation Maryland INTERNATIONAL Taiwan Corporate Headquarters Bethesda Taipei Tel: 408.433.8000 Tel: 301.897.5800 France LSI Logic Asia, Inc. Fax: 408.433.8989 Fax: 301.897.8389 Paris Taiwan Branch LSI Logic S.A. Tel: 886.2.2718.7828 NORTH AMERICA Massachusetts Immeuble Europa Fax: 886.2.2718.8869 ♦...
  • Page 213 Fax: 86.10.6804.2521 Acal Nederland b.v. Tel: 31.40.2.502602 France Fax: 31.40.2.510255 Rungis Cedex Azzurri Technology France Switzerland Tel: 33.1.41806310 Brugg Fax: 33.1.41730340 LSI Logic Sulzer AG Tel: 41.32.3743232 Germany Fax: 41.32.3743233 Haar EBV Elektronik Taiwan Tel: 49.89.4600980 Taipei Fax: 49.89.46009840 Avnet-Mercuries...

Table of Contents