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4-14
Register: 0xFC10
DMA Status (DS)
Read/Write
7
R
0
0
The DMA function in the SYM53C040 provides the capability of
transferring up to 256 bytes from memory to the SCSI port or vice versa.
The DMA function is designed to handshake automatically with the SCSI
core, to offload the microcontroller and increase SCSI throughput. The
DS register provides basic control of the DMA function, the
Length (DTL)
register sets the 8-bit transfer length (1 to 256), and the
DMA Source/Destination Low (DSDL)
Source/Destination High (DSDH)
source or destination address for the data to be transferred. The DMA
function does not provide any additional capability for handling SCSI
protocol, so all phase changes and error conditions must still be handled
manually by the microcontroller. The DMA direction is based solely on
the SCSI I/O phase lines.
R
Reserved
IOD
I/O Direction
This status bit will indicate the current DMA direction.
This bit is written by the microcontroller. A high on this bit
indicates the DMA is reading bytes from the SCSI core
and writing them to memory. A low on this bit indicates
the DMA is reading bytes from memory and writing them
to the SCSI core.
TC
Transfer Complete
This read only status bit will read a 1 following the normal
completion of a DMA transfer.
R
Reserved
IEN
Interrupt Enable
When this bit is set to a 1, the DMA function will generate
an interrupt whenever the TIP bit transitions from a 1 to
a 0. This signifies that (1) the transfer completed
SCSI and DMA Registers
5
4
3
IOD
TC
Defaults:
0
x
x
(0xFC12) and
(0xFC13) registers set the 16-bit
2
1
0
R
IEN
TIP
0
x
x
DMA Transfer
DMA
[7:5]
4
3
2
1
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