LSI LSI53C875A Technical Manual

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TECHNICAL

MANUAL

LSI53C875A

PCI to Ultra SCSI

Controller

Version 2.0

D e c e m b e r 2 0 0 0

S14047

Table of Contents

Chapters

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Page 1 TECHNICAL MANUAL LSI53C875A PCI to Ultra SCSI Controller Version 2.0 D e c e m b e r 2 0 0 0 ® S14047...
Page 2 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.
Page 3 Preface This book is the primary reference and technical manual for the LSI53C875A PCI to Ultra SCSI Controller. It contains a complete functional description for the product and also includes complete physical and electrical specifications. Audience This manual provides reference information on the LSI53C875A PCI to Ultra SCSI Controller.
Page 4 Chapter 6, Electrical Specifications characteristics and AC timing diagrams. Appendix A, Register Summary Appendix B, External Memory Interface Diagram Examples several example interface drawings for connecting the LSI53C875A to external ROMs. Related Publications For background information, please contact: ANSI 11 West 42nd Street...
Page 5 PCI Special Interest Group 2575 N.E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344 Conventions Used in This Manual The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Hexadecimal numbers are indicated by the prefix “0x”...
Page 6 Preface...
Page 7: Table Of Contents
Contents Chapter 1 General Description New Features in the LSI53C875A Benefits of Ultra SCSI TolerANT LSI53C875A Benefits Summary 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 Chapter 2 Functional Description PCI Functional Description 2.1.1 2.1.2 2.1.3 SCSI Functional Description 2.2.1 2.2.2 2.2.3...
Page 8 Chained Block Moves Default Download Mode No Download Mode Power State D0 Power State D1 Power State D2 Power State D3 Internal Pull-ups on LSI53C875A Signals System Signals Address and Data Signals Interface Control Signals Arbitration Signals Error Reporting Signals Interrupt Signal...
Page 9 Chapter 4 Registers PCI Configuration Registers SCSI Registers 64-Bit SCRIPTS Selectors Phase Mismatch Jump Registers Chapter 5 SCSI SCRIPTS Instruction Set Low Level Register Interface Mode High Level SCSI SCRIPTS Mode 5.2.1 Block Move Instruction 5.3.1 5.3.2 I/O Instruction 5.4.1 5.4.2 Read/Write Instructions 5.5.1...
Page 10 Typical LSI53C875A System Application Typical LSI53C875A Board Application LSI53C875A Block Diagram Parity Checking/Generation DMA FIFO Sections LSI53C875A Host Interface SCSI Data Paths Regulated Termination for Ultra SCSI Determining the Synchronous Transfer Rate Block Move and Chained Block Move Instructions LSI53C875A Functional Signal Grouping...
Page 11 Target Asynchronous Send 6.36 Target Asynchronous Receive 6.37 Initiator and Target Synchronous Transfer 6.38 LSI53C875A 160-Pin PQFP Mechanical Drawing 6.39 169-Pin BGA Mechanical Drawing 16 Kbyte Interface with 200 ns Memory 64 Kbyte Interface with 150 ns Memory Contents 6-13...
Page 12 Bits Used for Parity Control and Generation SCSI Parity Control SCSI Parity Errors and Interrupts Parallel ROM Support Mode A Serial EEPROM Data Format Power States LSI53C875A Internal Pull-ups System Signals Address and Data Signals Interface Control Signals Arbitration Signals Error Reporting Signals...
Page 13 SCSI Information Transfer Phase Read/Write Instructions Transfer Control Instructions SCSI Phase Comparisons Absolute Maximum Stress Ratings Operating Conditions Input Capacitance Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/, MWE/ Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO[2:4] Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR Input Signals—CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI, TEST_HSC, TEST_RST, TMS, TRST/ Output Signal—TDO...
Page 14 20.0 Mbytes (16-Bit Transfers) 40 MHz Clock Ultra SCSI Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 160 PQFP Pin List by Location 169 BGA Pin List by Location LSI53C875A PCI Register Map LSI53C875A SCSI Register Map 6-38 6-42 6-43...
Page 15: Chapter 1 General Description
It supports Ultra SCSI transfer rates with Single-Ended (SE) signaling for SCSI devices. The LSI53C875A has a local memory bus for local storage of the device’s BIOS ROM in flash memory or standard EEPROMs. The LSI53C875A supports programming of local flash memory for updates to BIOS.
Page 16: Typical Lsi53C875A System Application
Figure 1.1 Typical LSI53C875A System Application PCI Bus PCI Bus Interface Controller Central Typical PCI Processing Computer System Unit Architecture (CPU) Figure 1.2 Typical LSI53C875A Board Application SCSI Data, Parity and Control 68 Pin Signals SCSI Wide Connector PCI Address, Data, Parity and Control Signals...
Page 17: New Features In The Lsi53C875A
1.1 New Features in the LSI53C875A The LSI53C875A is a drop-in replacement for the LSI53C875 PCI to Ultra SCSI Controller, with these additional benefits: Supports 32-bit PCI Interface with 64-bit addressing. Handles SCSI phase mismatches in SCRIPTS without interrupting the CPU.
Page 18: Tolerant ® Technology
TolerANT technology is compatible with both the Alternative One and Alternative Two termination schemes proposed by the American National Standards Institute. 1.4 LSI53C875A Benefits Summary This section of the chapter provides an overview of the LSI53C875A features and benefits. It contains these topics: SCSI Performance PCI Performance...
Page 19: Scsi Performance
Flexibility Reliability Testability 1.4.1 SCSI Performance To improve SCSI performance, the LSI53C875A: Has integrated SE transceivers. Bursts up to 512 bytes across the PCI bus through its 944 byte FIFO. Performs wide, Ultra SCSI synchronous transfers as fast as 40 Mbytes/s.
Page 20: Memory Move Instructions 5
Supports PCI Write and Invalidate, Read Line, and Read Multiple commands. Complies with PCI Bus Power Management Specification Rev 1.1. 1.4.3 Integration Features of the LSI53C875A which ease integration include: High-performance SCSI core. Integrated SE transceivers. Full 32-bit PCI DMA bus master.
Page 21: Flexibility
Support for relative jumps. SCSI Selected as ID bits for responding with multiple IDs. 1.4.5 Flexibility The LSI53C875A provides: High level programming interface (SCSI SCRIPTS). Ability to program local and bus flash memory. Selectable 112 or 944 byte DMA FIFO for backward compatibility.
Page 22: Reliability
Ability to route system clock to SCSI clock. Compatible with 3.3 V and 5 V PCI. 1.4.6 Reliability Enhanced reliability features of the LSI53C875A include: 2 kV ESD protection on SCSI signals. Protection against bus reflections due to impedance mismatches.
Page 23: Chapter 2 Functional Description
Section 2.2, “SCSI Functional Description” Section 2.3, “Parallel ROM Interface” Section 2.4, “Serial EEPROM Interface” Section 2.5, “Power Management” The LSI53C875A PCI to Ultra SCSI Controller is composed of the following modules: 32-bit PCI Interface with 64-bit addressing PCI-to-Wide Ultra SCSI Controller...
Page 24: Pci Functional Description
Processor SCSI FIFO and SCSI Control Block JTAG JTAG Bus 2.1 PCI Functional Description The LSI53C875A implements a PCI-to-Wide Ultra SCSI controller. 2.1.1 PCI Addressing There are three physical PCI-defined address spaces: PCI Configuration space. I/O space for operating registers.
Page 25: Pci Bus Commands And Functions Supported
AD[10:8] are reserved for multifunction devices. At initialization time, each PCI device is assigned a base address for I/O and memory accesses. In the case of the LSI53C875A, the upper 24 bits of the address are selected. On every access, the LSI53C875A compares its assigned base addresses with the value on the Address/Data bus during the PCI address phase.
Page 26: Pci Bus Commands And Encoding Types For The Lsi53C875A
2. See the Chip Test Three (CTEST3) 2.1.2.1 Interrupt Acknowledge Command The LSI53C875A does not respond to this command as a slave and it never generates this command as a master. 2.1.2.2 Special Cycle Command The LSI53C875A does not respond to this command as a slave and it never generates this command as a master.
Page 27 The I/O Write command writes data to an agent mapped in I/O address space. All 32 address bits are decoded. 2.1.2.5 Reserved Command The LSI53C875A does not respond to this command as a slave and it never generates this command as a master. 2.1.2.6 Memory Read Command The Memory Read command reads data from an agent mapped in the Memory Address Space.
Page 28 This command is identical to the Memory Read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. The LSI53C875A supports PCI Memory Read Multiple functionality and issues Memory Read Multiple commands on the PCI bus when the Read Multiple Mode is enabled.
Page 29 The Read Line function in the LSI53C875A takes advantage of the PCI 2.2 specification regarding issuing this command.
Page 30 4. The chip is aligned to a cache line boundary. When these conditions are met, the LSI53C875A issues a Memory Write and Invalidate command instead of a Memory Write command during all PCI write cycles.
Page 31: Pci Cache Mode
Latency – In accordance with the PCI specification, the latency timer is ignored when issuing a Memory Write and Invalidate command such that when a latency time-out occurs, the LSI53C875A continues to transfer up to a cache line boundary. At that point, the chip relinquishes the bus, and finishes the transfer at a later time using another bus ownership.
Page 32 software enabled or disabled to allow the user full flexibility in using these commands. 2.1.3.1 Enabling Cache Mode In order to enable the cache logic to issue PCI cache commands (Memory Read Line, Memory Read Multiple, and Memory Write and Invalidate) on any given PCI master operation the following conditions must be met: The Cache Line Size Enable bit in the...
Page 33 To issue Memory Read Multiple commands, the Read Multiple enable bit in the To issue Memory Write and Invalidate commands, both the Write and Invalidate enables in the PCI configuration command register must be set. If the corresponding cache command being issued is not enabled then the cache logic falls back to the next command enabled.
Page 34: Pci Cache Mode Alignment
Multiple Memory Write and Invalidates. A single data residual Memory Write to complete the transfer. Table 2.2 Table 2.2 2-12 Functional Description describes PCI cache mode alignment. PCI Cache Mode Alignment Host Memory...
Page 35 2.1.3.5 Examples: MR = Memory Read, MRL = Memory Read Line, MRM = Memory Read Multiple, MW = Memory Write, MWI = Memory Write and Invalidate. Read Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords: A to B: A to C: A to D:...
Page 36 C to E: D to F: A to H: A to G: Read Example 3 – Burst = 16 Dwords, Cache Line Size = 8 Dwords: A to B: A to C: A to D: C to D: C to E: D to F: A to H: A to G:...
Page 37 D to F: MW (15 bytes) MWI (16 bytes) MW (1 byte) A to H: MW (15 bytes) MWI (16 bytes) MWI (16 bytes) MWI (16 bytes) MWI (16 bytes) MW (2 bytes) A to G: MW (15 bytes) MWI (16 bytes) MWI (16 bytes) MWI (16 bytes) MW (3 bytes)
Page 38: Scsi Functional Description
SCSI SCRIPTS, making it easy to “fine tune” the system for specific mass storage devices or Ultra SCSI requirements. The LSI53C875A offers low level register access or a high-level control interface. Like first generation SCSI devices, the LSI53C875A is 2-16...
Page 39: Scripts Processor
SCSI bus. In support of SCSI loopback diagnostics, the SCSI core may perform a self-selection and operate as both an initiator and a target. The LSI53C875A is controlled by the integrated SCRIPTS processor through a high-level logical interface. Commands controlling the SCSI core are fetched out of the main host memory or local memory.
Page 40: Internal Scripts Ram
2.2.2 Internal SCRIPTS RAM The LSI53C875A has 4 Kbyte (1024 x 32 bits) of internal, general purpose RAM. The RAM is designed for SCRIPTS program storage, but is not limited to this type of information. When the chip fetches SCRIPTS instructions or Table Indirect information from the internal RAM, these fetches remain internal to the chip and do not use the PCI bus.
Page 41: 64-Bit Addressing In Scripts
GPIO_0 pin. The CON (Connected) bit in the LSI53C875A is connected to the SCSI bus either as an initiator or a target. This will happen after the LSI53C875A has successfully completed a selection or when it has successfully responded to a selection or reselection.
Page 42: Designing An Ultra Scsi System
Ultra design. 2.2.5.1 Using the SCSI Clock Quadrupler The LSI53C875A can quadruple the frequency of a 20 MHz SCSI clock, allowing the system to perform Ultra SCSI transfers. This option is user selectable with bit settings in the...
Page 43: Prefetching Scripts Instructions
Memory Read Line, and Memory Read Multiple, if PCI caching is enabled. Note: The LSI53C875A may flush the contents of the prefetch unit under certain conditions, listed below, to ensure that the chip always operates from the most current version of the SCRIPTS instruction. When one of these conditions apply, the contents of the prefetch unit are automatically flushed.
Page 44: Transfer Control Instructions 5
Functional Description DMA SCRIPTS Pointer (DSP) (DMA Control (DCNTL) register (0x38) causes the LSI53C875A to burst in the first two This feature is only useful if Prefetching is disabled and SCRIPTS instructions are fetched from main memory. Due to the short SCRIPTS RAM access time, burst opcode fetching is not necessary when fetching instructions from this memory.
Page 45: Jtag Boundary Scan Testing
When the Loopback Enable bit is set in the register, bit 4, the LSI53C875A allows control of all SCSI signals whether the chip is operating in the initiator or target mode. For more information on this mode of operation refer to the LSI Logic SCSI SCRIPTS Processor Programming Guide.
Page 46: Parity Options
2.2.11 Parity Options The LSI53C875A implements a flexible parity scheme that allows control of the parity sense, allows parity checking to be turned on or off, and has the ability to deliberately send a byte with bad parity over the SCSI bus to test parity error recovery procedures.
Page 47: Bits Used For Parity Control And Generation
Determines whether the LSI53C875A generates an interrupt when it detects a SCSI parity error. This status bit is set whenever the LSI53C875A detects a parity error on the SCSI bus. This status bit represents the active HIGH current state of the SCSI SDP0 parity signal.
Page 48: Scsi Parity Control
Table 2.4 SCSI Parity Control ASEP 1. EPC = Enable Parity Checking (bit 3 2. ASEP = Assert SCSI Even Parity (bit 2 Table 2.5 SCSI Parity Errors and Interrupts 1. DHP = Disable Halt on SATN/ or Parity Error (bit 5 2.
Page 49: Dma Fifo
Figure 2.2 Parity Checking/Generation Asynchronous Asynchronous SCSI Send SCSI Receive PCI Interface** PCI Interface** DMA FIFO* DMA FIFO* (64 bits X 118) (64 bits X 118) SIDL Register* SODL Register* SCSI Interface** SCSI Interface** X = Check parity G = Generate 32-bit even PCI parity S = Generate 8-bit odd SCSI parity 2.2.12 DMA FIFO The DMA FIFO is 8 bytes wide by 118 transfers deep.
Page 50: Dma Fifo Sections
Byte Lane 7 Byte Lane 6 The LSI53C875A automatically supports misaligned DMA transfers. A 944-byte FIFO allows the LSI53C875A to support 2, 4, 8, 16, 32, 64, or 128 Dword bursts across the PCI bus interface. 2.2.12.1 Data Paths The data path through the LSI53C875A is dependent on whether data is being moved into or out of the chip, and whether SCSI data is being transferred asynchronously or synchronously.
Page 51: Lsi53C875A Host Interface Scsi Data Paths
Figure 2.4 LSI53C875A Host Interface SCSI Data Paths Asynchronous Asynchronous SCSI Send SCSI Receive PCI Interface** PCI Interface** DMA FIFO* DMA FIFO* (8 Bytes x 118) (8 Bytes x 118) SIDL Register* SODL Register* SCSI Interface** SCSI Interface** The following steps determine if any bytes remain in the data path when the chip halts an operation: Asynchronous SCSI Send –...
Page 52 Step 2. Read bit 5 in the Synchronous SCSI Send – Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Step 2. Read bit 5 in the Step 3. Read bit 6 in the 2-30 Functional Description bits of the DBC register from the 10-bit value of the DMA FIFO...
Page 53 then the least significant byte or the most significant byte in the SODR register is full, respectively. Asynchronous SCSI Receive – Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Five (CTEST5) register cleared), look at the (DFIFO) DMA Byte Counter (DBC) if there are bytes left in the DMA FIFO.
Page 54: Scsi Bus Interface
Due to the high Figure 2.5 shows a Unitrode active terminator. For If the LSI53C875A is used with an 8-bit SCSI bus, all 16 data lines must still be terminated or pulled HIGH. Active termination is required for Ultra SCSI synchronous transfers.
Page 55: Select/Reselect During Selection/Reselection
Figure 2.5 Regulated Termination for Ultra SCSI 2.85 V REG_OUT DISCONNECT REG_OUT DISCONNECT Note: 1. C1 - 10 F SMT 2. C2 - 0.1 F SMT 3. C3 - 2.2 F SMT 4. J1 - 68-pin, high density “P” connector 2.2.14 Select/Reselect During Selection/Reselection In multithreaded SCSI I/O environments, it is not uncommon to be selected or reselected while trying to perform selection/reselection.
Page 56: Synchronous Operation
Set Target instruction. The Selection and Reselection Enable bits (SCSI Chip ID (SCID) so that the LSI53C875A may respond as an initiator or as a target. If only selection is enabled, the LSI53C875A cannot be reselected as an initiator.
Page 57: Determining The Synchronous Transfer Rate
Synchronous send rate must not exceed 20 Mbytes/s because the LSI53C875A is an Ultra SCSI device. Although maximum synchronous receive rate is 40 Mbytes/s the maximum transfer rate is 20 Mbytes/s because the LSI53C875A is an Ultra SCSI device. SCSI Functional Description...
Page 58 50 ns, which is half the 100 ns period allowed under Fast SCSI-2. This allows a maximum transfer rate of 40 Mbytes/s on a 16-bit SCSI bus. The LSI53C875A has a SCSI clock quadrupler that must be enabled for the chip to perform Ultra SCSI transfers with a 20 or 40 MHz oscillator.
Page 59: Interrupt Handling
A hybrid approach would use hardware interrupts for long waits, and use polling for short waits. 2.2.16.2 Registers The registers in the LSI53C875A that are used for detecting or defining interrupts are (ISTAT1), Status Zero...
Page 60 DMA FIFO to memory before generating the interrupt. If the LSI53C875A is sending data to the SCSI bus and a fatal SCSI interrupt condition occurs, data could be left in the DMA FIFO. Because of this the DMA FIFO Empty (DFE) bit in checked.
Page 61 Some SCSI interrupts (indicated by the SIP bit in the Zero (ISTAT0) (SIST0) When the LSI53C875A is operating in the Initiator mode, only the Function Complete (CMP), Selected (SEL), Reselected (RSL), General SCSI Functional Description DMA Status (DSTAT)
Page 62 CPU. This prevents an interrupt when arbitration is complete (CMP set), when the LSI53C875A is selected or reselected (SEL or RSL set), when the initiator asserts ATN (target mode: SATN/ active), or when the General Purpose or Handshake-to-Handshake timers expire.
Page 63 IRQ/. 2.2.16.5 Stacked Interrupts The LSI53C875A will stack interrupts if they occur one after the other. If the SIP or DIP bits in the ISTAT register are set (first level), then there is already at least one pending interrupt, and any future interrupts are...
Page 64 These ‘locked out’ SCSI interrupts are posted as soon as the DMA FIFO is empty. 2.2.16.6 Halting in an Orderly Fashion When an interrupt occurs, the LSI53C875A attempts to halt in an orderly fashion. If the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a Bus Fault.
Page 65 All other instructions may halt before completion. 2.2.16.7 Sample Interrupt Service Routine The following is a sample of an interrupt service routine for the LSI53C875A. It can be repeated during polling or should be called when the IRQ/ pin is asserted during hardware interrupts. 1. Read 2.
Page 66: Chained Block Moves
2.2.17 Chained Block Moves Since the LSI53C875A has the capability to transfer 16-bit wide SCSI data, a unique situation occurs when dealing with odd bytes. The Chained Move (CHMOV) SCRIPTS instruction along with the Wide SCSI Send (WSS) and Wide SCSI Receive (WSR) bits in the...
Page 67: Block Move And Chained Block Move Instructions
Figure 2.7 0x03 0x07 0x0B 0x0F 0x13 2.2.17.1 Wide SCSI Send Bit The WSS bit is set whenever the SCSI controller is sending data (Data-Out for initiator or Data-In for target) and the controller detects a partial transfer at the end of a chained Block Move SCRIPTS instruction (this flag is not set if a normal Block Move instruction is used).
Page 68 two bytes are sent out across the bus, regardless of the type of Block Move instruction (normal or chained). The flag is automatically cleared when the “married” word is sent. The flag is alternately cleared through SCRIPTS or by the microprocessor. Also, the microprocessor or SCRIPTS can use this bit for error detection and recovery purposes.
Page 69 2.2.17.5 Chained Block Move SCRIPTS Instruction A chained Block Move SCRIPTS instruction is primarily used to transfer consecutive data send or data receive blocks. Using the chained Block Move instruction facilitates partial receive transfers and allows correct partial send behavior without additional opcode overhead. Behavior of the chained Block Move instruction varies slightly for sending and receiving data.
Page 70: Parallel Rom Interface
Moves five bytes from address 0x09 in the host memory to the SCSI bus. 2.3 Parallel ROM Interface The LSI53C875A supports up to one megabyte of external memory in binary increments from 16 Kbytes, to allow the use of expansion ROM for add-in PCI cards.
Page 71: Parallel Rom Support
Note: There are internal pull-downs on all of the MAD bus signals. The LSI53C875A allows the system to determine the size of the available external memory using the Expansion ROM Base Address PCI configuration space. For more information on how this works, refer...
Page 72: Serial Eeprom Interface
2.4 Serial EEPROM Interface The LSI53C875A implements an interface that allows attachment of a serial EEPROM device to the GPIO0 and GPIO1 pins. There are two modes of operation relating to the serial EEPROM and the Subsystem ID and Subsystem Vendor ID registers. These modes are programmable through the MAD7 pin which is sampled at power-up.
Page 73: No Download Mode
PCI specification, with a default value of 0x1000 and 0x1000 respectively. 2.5 Power Management The LSI53C875A complies with the PCI Bus Power Management Interface Specification, Revision 1.1. The PCI Function Power States D0, D1, D2, and D3 are defined in that specification.
Page 74: Power State D0
Power state D1 is a lower power state than D0. In this state, the LSI53C875A core is placed in the snooze mode and the SCSI CLK is disabled. In the snooze mode, a SCSI reset does not generate an IRQ/ signal.
Page 75: Power State D2
2.5.3 Power State D2 Power state D2 is a lower power state than D1. In this state the LSI53C875A core is placed in the coma mode. The following PCI Configuration Space command register enable bits are suppressed: I/O Space Enable...
Page 76 2-54 Functional Description...
Page 77: Chapter 3 Signal Descriptions
Chapter 3 Signal Descriptions This chapter presents the LSI53C875A pin configuration and signal definitions using tables and illustrations. This chapter contains the following sections: Section 3.1, “LSI53C875A Functional Signal Grouping” Section 3.2, “Signal Descriptions” Section 3.3, “PCI Bus Interface Signals”...
Page 78: Lsi53C875A Functional Signal Grouping
Address Data Interface Control Arbitration Error Reporting Interrupt SCSI Function GPIO ROM Flash & Memory Interface Signal Descriptions presents the LSI53C875A signals by functional group. LSI53C875A RST/ SCLK AD[31:0] SD[15:0] C_BE[3:0]/ SDP[1:0] FRAME/ TRDY/ IRDY/ STOP/ DEVSEL/ SMSG IDSEL SREQ...
Page 79: Signal Descriptions
The SCSI Bus Interface Signals are subdivided into Signals, Signals are assigned a type. There are five signal types: S/T/S 3.2.1 Internal Pull-ups on LSI53C875A Signals Several signals in the LSI53C875A have internal pull-up resistors. Table 3.1 Table 3.1 LSI53C875A Internal Pull-ups Signal Name...
Page 80: Pci Bus Interface Signals
3.3 PCI Bus Interface Signals The PCI Bus Interface Signals section contains tables describing the signals for the following signal groups: Data Signals, Reporting 3.3.1 System Signals Table 3.2 Table 3.2 System Signals Name PQFP Type Strength Description RST/ Signal Descriptions Interface Control Signals, Signals, and...
Page 81: Address And Data Signals
3.3.2 Address and Data Signals Table 3.3 Table 3.3 Address and Data Signals Name PQFP AD[31:0] 150, 151, B5, C5, A4, 153, 154, B4, A3, C4, 156, 157, D4, A2, C2, 159, 160, 3, E5, C1, D3, 5, 6, 7, 9, E4-E1, H5, 11–13, 28–...
Page 82: Interface Control Signals
3.3.3 Interface Control Signals Table 3.4 Table 3.4 Interface Control Signals Name PQFP BGA Type FRAME/ S/T/S 8 mA PCI Cycle Frame is driven by the current master to indicate TRDY/ S/T/S 8 mA PCI Target Ready indicates the target agent’s (selected IRDY/ S/T/S 8 mA PCI Initiator Ready indicates the initiating agent’s (bus STOP/...
Page 83: Arbitration Signals
3.3.4 Arbitration Signals Table 3.5 Table 3.5 Arbitration Signals Name PQFP BGA Type Strength Description REQ/ GNT/ 3.3.5 Error Reporting Signals Table 3.6 Table 3.6 Error Reporting Signals Name PQFP BGA Type PERR/ S/T/ SERR/ PCI Bus Interface Signals describes Arbitration signals. 8 mA PCI Request indicates to the system arbiter that this agent desires use of the PCI bus.
Page 84: Interrupt Signal
3.3.6 Interrupt Signal Table 3.7 Table 3.7 Interrupt Signal Name PQFP BGA Type IRQ/ 1. See Register 0x4D, SCSI Test One (STEST1) 3.4 SCSI Bus Interface Signals The SCSI Bus Interface signals section contains tables describing the signals for the following signal groups: Signals, and 3.4.1 SCSI Bus Interface Signal Table 3.8...
Page 85: Scsi Signals
3.4.2 SCSI Signals Table 3.9 Table 3.9 SCSI Signals Name PQFP SD[15:0] 113, 115–17, 85–87, 89, 102, 103, 105–108, 110, SDP[1:0] 112, 101 3.4.3 SCSI Control Signals Table 3.10 Table 3.10 SCSI Control Signals Name PQFP BGA Type Strength Description SMSG 95 SREQ 91 SACK...
Page 86: Gpio Signals
EEPROM interface. This signal can also be programmed to be driven LOW when the LSI53C875A is active on the SCSI bus. 8 mA SCSI General Purpose I/O pin. Optionally, when driven LOW, indicates that the LSI53C875A is bus master.
Page 87: Rom Flash And Memory Interface Signals
Memory Output Enable. This pin is used as an output enable signal to an external EEPROM or flash memory during read operations. It is also used to test the connectivity of the LSI53C875A signals in test mode. 16 mA Memory Access Control. This pin can be programmed to indicate local or system memory accessed (non-PCI applications).
Page 88: Test Interface Signals
EEPROM/ flash memory. These pins have static pull-downs. describes Test Interface signals. Test Halt SCSI Clock. For LSI Logic test purposes only. Pulled HIGH internally. This signal can also cause a full chip reset.
Page 89: Power And Ground Signals
3.8 Power and Ground Signals Table 3.14 Table 3.14 Power and Ground Signals Name PQFP VSS_I/O 4, 10, 14, 18, 23, 27, 31, 37, 42, 48, 69, 79, 88, 93, 99, 104, 109, 114, 123, 133, 152, VDD_I/O 8, 21, 33, 45, 63, 74, 84, 118, 128, 138, VDD_CORE 51, 83, 149...
Page 90: Mad Bus Programming
3.9 MAD Bus Programming The MAD[7:0] pins, in addition to serving as the address/data bus for the local memory interface, also are used to program power-up options for the chip. A particular option is programmed allowing the internal pull-down current sink to pull the pin LOW at reset or by connecting a 4.7 k pull-down resistors require that HC or HCT external components are used for the memory interface.
Page 91 The MAD[0] pin is the slow ROM pin. When pulled up, it enables two extra cycles of data access time to allow use of slower memory devices. All MAD pins have internal pull-down resistors. MAD Bus Programming 3-15...
Page 92 3-16 Signal Descriptions...
Page 93: Chapter 4 Registers
Chapter 4 Registers This chapter describes all LSI53C875A registers and is divided into the following sections: Section 4.1 “PCI Configuration Registers” Section 4.2 “SCSI Registers” Section 4.3 “64-Bit SCRIPTS Selectors” Section 4.4 “Phase Mismatch Jump Registers” In the register descriptions, the term “set” is used to refer to bits that are programmed to a binary one.
Page 94: Pci Configuration Register Map
LSI53C875A are described in this chapter. Reserved bits should not be accessed Table 4.1 PCI Configuration Register Map Device ID Status Class Code Not Supported Header Type Base Address Register One (MEMORY) Base Address Register Two (SCRIPTS RAM)
Page 95 Command register provides coarse control over a device’s ability to generate and respond to PCI cycles. When a zero is written to this register, the LSI53C875A is logically disconnected from the PCI bus for all accesses except configuration accesses. Reserved SERR/ Enable This bit enables the SERR/ driver.
Page 96 Write and Invalidate commands. Reserved Enable Bus Mastering This bit controls the ability of the LSI53C875A to act as a master on the PCI bus. A value of zero disables this device from generating PCI bus master accesses. A value of one allows the LSI53C875A to behave as a bus master.
Page 97 15 and not affect any other bits, write the value 0x8000 to the register. Detected Parity Error (from Slave) This bit is set by the LSI53C875A whenever it detects a data parity error, even if data parity error handling is disabled.
Page 98 These bits are read only and should indicate the slowest time that a device asserts DEVSEL/ for any bus command except Configuration Read and Configuration Write. The LSI53C875A supports a value of 0b01. Data Parity Error Reported This bit is set when all of the following conditions are met: The bus agent asserted PERR/ itself or observed PERR/ asserted.
Page 99 Registers: 0x09–0x0B Class Code Read Only Register: 0x0C Cache Line Size Read/Write PCI Configuration Registers Class Code This 24-bit register is used to identify the generic function of the device. The upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identifies a specific register level programming interface.
Page 100 The Latency Timer register specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. The LSI53C875A supports this timer. All eight bits are writable, allowing latency values of 0–255 PCI clocks. Use the following equation to calculate an optimum latency value for the LSI53C875A.
Page 101 Base Address Register Zero - I/O This base address register is used to map the operating register set into I/O space. The LSI53C875A requires 256 bytes of I/O space for this base address register. It has bit zero hardwired to one. Bit 1 is reserved and returns a zero on all reads, and the other bits are used to map the device into I/O space.
Page 102 This base register is used to map the SCRIPTS RAM into memory space. The default value of this register is 0x00000000. The LSI53C875A points to 4096 bytes of address space with this register. This register has bits [11:0] hardwired to 0b000000000000. For detailed information on the operation of this register, refer to the PCI 2.2 specification.
Page 103 If the external serial EEPROM interface is disabled (MAD[7] HIGH), this register returns a value of 0x1000 (LSI Logic Vendor ID). The 16-bit value that should be stored in the external serial EEPROM for this register is the vendor’s PCI Vendor ID and must be obtained from the PCI Special Interest Group (SIG).
Page 104 Expansion ROM Base Address with all ones and then reading back the register. The LSI53C875A responds with zeros in all don’t care locations. The ones in the remaining bits represent the binary version of the external memory size. For example,...
Page 105 Register: 0x34 Capabilities Pointer Read Only Capabilities Pointer This register indicates that the first extended capability register is located at offset 0x40 in the PCI Configuration. Registers: 0x35–0x3B Reserved Register: 0x3C Interrupt Line Read/Write Interrupt Line This register is used to communicate interrupt line routing information.
Page 106 Max_Lat is used to specify how often the device needs to gain access to the PCI bus. The value specified in this register is in units of 0.25 microseconds. The LSI53C875A sets this register to 0x40. [7:0]...
Page 107 PMES PME_Support Bits [15:11] define the power management states in which the LSI53C875A will assert the PME pin. These bits are all set to zero because the LSI53C875A does not provide a PME signal. PCI Configuration Registers DSI APS PMEC...
Page 108 Read/Write 14 13 12 PST DSCL 4-16 Registers D2_Support The LSI53C875A sets this bit to indicate support for power management state D2. D1_Support The LSI53C875A sets this bit to indicate support for power management state D1. Reserved Device Specific Initialization...
Page 109 DSLT Data_Select The LSI53C875A does not support the data register. Therefore, these four bits are always cleared. PME_Enable The LSI53C875A always returns a zero for this bit to indicate that PME assertion is disabled. Reserved PWS[1:0] Power State Bits [1:0] are used to determine the current power state of the LSI53C875A.
Page 110: Scsi Registers
DATA Data This register provides an optional mechanism for the function to report state-dependent operating data. The LSI53C875A does not use this register and always returns 0x00. Table 4.2. The only registers that the host CPU can access while the...
Page 111: Scsi Register Address Map
Table 4.2 SCSI Register Address Map SCNTL3 GPREG0 SBCL SSTAT2 MBOX1 CTEST3 CTEST6 DCMD DCNTL SIST1 GPCNTL0 RESPID1 RESPID0 STEST3 Reserved CCNTL1 Reserved Reserved SCSI Registers 16 15 SCNTL2 SCNTL1 SDID SXFER SSID SOCL SSTAT1 SSTAT0 MBOX0 ISTAT1 CTEST2 CTEST1 TEMP CTEST5 CTEST4...
Page 112 ARB1 ARB0 Full arbitration, selection/reselection Simple Arbitration 1. The LSI53C875A waits for a bus free condition to occur. 2. It asserts SBSY/ and its SCSI ID (contained in the SCSI Chip ID (SCID) the SSEL/ signal is asserted by another SCSI device,...
Page 113 SCSI bus. 3. If the SSEL/ signal is asserted by another SCSI device or if the LSI53C875A detects a higher priority ID, the LSI53C875A deasserts SBSY, deasserts its ID, and waits until the next bus free state to try arbitration again.
Page 114 Registers Select with SATN/ on a Start Sequence When this bit is set and the LSI53C875A is in the initiator mode, the SATN/ signal is asserted during selection of a SCSI target device. This is to inform the target that the LSI53C875A has a message to send.
Page 115 Setting this bit only affects SCSI send operations. Assert SCSI Data Bus When this bit is set, the LSI53C875A drives the contents of the SCSI Output Data Latch (SODL) SCSI data bus. When the LSI53C875A is an initiator, the SCSI I/O signal must be inactive to assert the SODL contents onto the SCSI bus.
Page 116 If the LSI53C875A is receiving data, any data residing in the DMA FIFO is sent to memory before halting. When this bit is set, the LSI53C875A does not halt the SCSI transfer when SATN/ or a parity error is received. Connected This bit is automatically set any time the LSI53C875A is connected to the SCSI bus as an initiator or as a target.
Page 117 Arbitration is retried until won. At that point, the LSI53C875A holds SBSY and SSEL asserted, and waits for a select or reselect sequence. The Immediate Arbitration bit is cleared automatically when the selection or reselection sequence is completed, or times out.
Page 118 Using chained mode facilitates partial receive transfers and allows correct partial send behavior. When this bit is set and a data transfer ends on an odd byte boundary, the LSI53C875A stores the last byte in SCSI Wide Residue (SWIDE) receive operation, or in the (SODL) register during a send operation.
Page 119 combined with the first byte from the subsequent transfer so that a wide transfer is completed. SLPMD SLPAR Mode If this bit is cleared, the register functions as a byte-wide longitudinal parity register. If this bit is set, the SLPAR functions as a word-wide longitudinal parity function.
Page 120 Setting this bit enables Ultra SCSI synchronous transfers. The default value of this bit is 0. This bit should remain cleared if the LSI53C875A is not operating in Ultra SCSI mode. When this bit is set, the signal filtering period for SREQ/...
Page 121 SCF2 SCF1 CCF2 CCF1 Note: It is important that these bits are set to the proper values to guarantee that the LSI53C875A meets the SCSI timings as defined by the ANSI specification. SCSI Registers SCSI Transfer SCF0 Factor SCSI Clock...
Page 122 Enable Response to Selection When this bit is set, the LSI53C875A is able to respond to bus-initiated selection at the chip ID in the RESPID0 and RESPID1 registers. Note that the chip does not automatically reconfigure itself to target mode as a result of being selected.
Page 123 The synchronous transfer period the LSI53C875A should use when transferring SCSI data is determined in the following example: The LSI53C875A is connected to a hard disk which can transfer data at 10 Mbytes/s synchronously. The LSI53C875A’s SCLK is running at 40 MHz. The...
Page 124: Examples Of Synchronous Transfer Periods And Rates For Scsi-1
Registers (This SCSI synchronous core clock is determined in SCNTL3 bits [6:4], ExtCC = 1 if SCNTL1 bit 7 is asserted and the LSI53C875A is sending data. ExtCC = 0 if the LSI53C875A is receiving data.) SXFERP = 100 25 = 4...
Page 125: Example Transfer Periods And Rates For Fast Scsi-2
1. Only with 40 MHz clock. MO[4:0] Max SCSI Synchronous Offset These bits describe the maximum SCSI synchronous offset used by the LSI53C875A when transferring synchronous SCSI data in either the initiator or target mode. Table 4.5 their relationship to the synchronous data offset used by the LSI53C875A.
Page 126: Maximum Synchronous Offset
Table 4.5 4-34 Registers Maximum Synchronous Offset Synchronous Offset 0-Asynchronous...
Page 127 Register: 0x06 SCSI Destination ID (SDID) Read/Write Reserved Encoded Destination SCSI ID Writing these bits set the SCSI ID of the intended initiator or target during SCSI reselection or selection phases, respectively. When executing SCRIPTS, the SCRIPTS processor writes the destination SCSI ID to this register. The SCSI ID is defined by the user in a SCRIPTS Select or Reselect instruction.
Page 128 EEPROM. GPIO1 is used as a clock, with the GPIO0 pin serving as data. LSI Logic software also reserves the use of GPIO[4:2]. If there is a need to use GPIO[4:2] please check with LSI Logic for additional information. SFBR...
Page 129 SCSI SCRIPTS. SOCL is used only when transferring data using programmed I/O. Some bits are set (1) or cleared (0) when executing SCSI SCRIPTS. Do not write to the register once the LSI53C875A starts executing normal SCSI SCRIPTS. SCSI Registers DMA Control (DCNTL) register is clear.
Page 130 Reserved Encoded Destination SCSI ID Reading the SSID register immediately after the LSI53C875A is selected or reselected returns the binary-encoded SCSI ID of the device that performed the operation. These bits are invalid for targets that are selected under the single initiator option of the SCSI-1 specification.
Page 131 Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the LSI53C875A stacks interrupts). The DIP bit in the Interrupt Status Zero (ISTAT0)
Page 132 4-40 Registers Master Data Parity Error This bit is set when the LSI53C875A as a master detects a data parity error, or a target device signals a parity error during a data phase. This bit is completely disabled by the Master Parity Error Enable bit (bit 3 of (CTEST4)).
Page 133 DMA Byte Counter (DBC) register while the LSI53C875A is in target mode. During a Transfer Control instruction, the Carry Test bit (bit 21) is set and either the Compare Data (bit 18) or Compare Phase (bit 17) bit is set.
Page 134 Register: 0x0D SCSI Status Zero (SSTAT0) Read Only 4-42 Registers SIDL Least Significant Byte Full This bit is set when the least significant byte in the Input Data Latch (SIDL) transferred from the SCSI bus to the SCSI Input Data Latch register before being sent to the DMA FIFO and then to the host bus.
Page 135 Arbitration in Progress Arbitration in Progress (AIP = 1) indicates that the LSI53C875A has detected a Bus Free condition, asserted SBSY, and asserted its SCSI ID onto the SCSI bus. Lost Arbitration When set, LOA indicates that the LSI53C875A has...
Page 136: Scsi Synchronous Data Fifo Word Count
Table 4.6 (SSTAT2 bit 4) 4-44 Registers synchronous data transfers, or up to 31 words for wide. Values over 31 will not occur. SCSI Synchronous Data FIFO Word Count Bytes or Words in the SCSI FIFO...
Page 137 Table 4.6 SCSI Synchronous Data FIFO Word Count (Cont.) (SSTAT2 bit 4) SDP0L Latched SCSI Parity This bit reflects the SCSI parity signal (SDP0/), corresponding to the data latched in the Latch (SIDL). It changes when a new byte is latched into the least significant byte of the SIDL register.
Page 138 Register: 0x0F SCSI Status Two (SSTAT2) Read Only ILF1 ILF1 ORF1 OLF1 4-46 Registers ORF1 OLF1 SIDL Most Significant Byte Full This bit is set when the most significant byte in the Input Data Latch (SIDL) from the SCSI bus to the SCSI Input Data Latch register before being sent to the DMA FIFO and then to the host bus.
Page 139 SCSI device selects or reselects the LSI53C875A. If the Connected bit is asserted and the LDSC bit is asserted, a disconnect is indicated. This bit is set when the Connected bit in SCNTL1 is off. This bit is cleared when a Block Move instruction is executed while the Connected bit in SCNTL1 is on.
Page 140 Interrupt Status Zero (ISTAT0) Read/Write ABRT This register is accessible by the host CPU while a LSI53C875A is executing SCRIPTS (without interfering in the operation of the function). It is used to poll for interrupts if hardware interrupts are disabled. Read this register after servicing an interrupt to check for stacked interrupts.
Page 141 LSI53C875A responds to a bus-initiated selection or reselection. It is also set after the LSI53C875A wins arbitration when operating in low level mode. When this bit is clear, the LSI53C875A is not connected to the SCSI bus. INTF Interrupt-on-the-Fly This bit is asserted by an INTFLY instruction during SCRIPTS execution.
Page 142 SCSI Interrupt Pending This status bit is set when an interrupt condition is detected in the SCSI portion of the LSI53C875A. The following conditions cause a SCSI interrupt to occur: A phase mismatch (initiator mode) or SATN/ becomes...
Page 143 A bus fault is detected An abort condition is detected A SCRIPTS instruction is executed in single step mode A SCRIPTS interrupt instruction is executed An illegal instruction is detected To determine exactly which condition(s) caused the interrupt, read the Register: 0x15 Interrupt Status One (ISTAT1) Read/Write...
Page 144 Register: 0x16 Mailbox Zero (MBOX0) Read/Write MBOX0 Note: Register: 0x17 Mailbox One (MBOX1) Read/Write MBOX1 Note: 4-52 Registers addition, this bit may be read and written while SCRIPTS are executing. MBOX0 Mailbox Zero These are general purpose bits that may be read or written while SCRIPTS are running.
Page 145 Register: 0x18 Chip Test Zero (CTEST0) Read/Write Byte Empty in DMA FIFO These bits identify the bottom bytes in the DMA FIFO that are empty. Each bit corresponds to a byte lane in the DMA FIFO. For example, if byte lane three is empty, then FMT3 will be set.
Page 146 Register: 0x1A Chip Test Two (CTEST2) Read Only (bit 3 write) DDIR DDIR SIGP Note: PCICIE 4-54 Registers SIGP PCICIE Data Transfer Direction This status bit indicates which direction data is being transferred. When this bit is set, the data is transferred from the SCSI bus to the host bus.
Page 147 TEOP SCSI True End of Process This bit indicates the status of the LSI53C875A’s TEOP signal. The TEOP signal acknowledges the completion of a transfer through the SCSI portion of the LSI53C875A. When this bit is set, TEOP is active. When this bit is clear, TEOP is inactive.
Page 148 (CTEST5) register, determines the direction of the transfer. This bit is not self-clearing; clear it once the data is successfully transferred by the LSI53C875A. Polling of FIFO flags is allowed during flush operations. Clear DMA FIFO When this bit is set, all data pointers for the DMA FIFO are cleared.
Page 149 Return instruction is executed. This address points to the next instruction to execute. Do not write to this register while the LSI53C875A is executing SCRIPTS. During any Memory-to-Memory Move operation, the contents of this register are preserved. The power-up value of this register is indeterminate.
Page 150 Note: 4-58 Registers while data is being transferred between the two cores. Once the chip has stopped transferring data, these bits are stable. DMA FIFO (DFIFO) bytes transferred between the DMA core and the SCSI core. The DMA Byte Counter (DBC) number of bytes transferred across the host bus.
Page 151 This bit is used with FBL[2:0]. See Bits [2:0] description in this register. SCSI Data High Impedance Setting this bit causes the LSI53C875A to place the SCSI data bus SD[15:0] and the parity lines SDP[1:0] in a high impedance state. In order to transfer data on the SCSI bus, clear this bit.
Page 152 ADCK 4-60 Registers LSI53C875A is informed of the error by the PERR/ pin being asserted by the target. When this bit is cleared, the LSI53C875A does not interrupt if a master parity error occurs. This bit is cleared at power-up.
Page 153 the current DBC value. This bit automatically clears itself after incrementing the DNAD register. BBCK Clock Byte Counter Setting this bit decrements the byte count contained in the 24-bit DBC register. It is decremented based on the DMA Byte Counter (DBC) Next Address (DNAD) itself after decrementing the DBC register.
Page 154 BO[9:8] Register: 0x23 Chip Test Six (CTEST6) Read/Write Registers: 0x24–0x26 DMA Byte Counter (DBC) Read/Write 4-62 Registers DMA FIFO Byte Offset Counter, Bits [9:8] These are the upper two bits of the DFBOC. The DFBOC consists of these bits, and the register, bits [7:0].
Page 155 Block Move and a value of 0x000000 is loaded into the DBC register, an illegal instruction interrupt occurs if the LSI53C875A is not in target mode, Command phase. The DBC register is also used to hold the least significant 24 bits of the first Dword of a SCRIPTS fetch, and to hold the offset value during table indirect I/O SCRIPTS.
Page 156 Registers: 0x28–0x2B DMA Next Address (DNAD) Read/Write DNAD Registers: 0x2C–0x2F DMA SCRIPTS Pointer (DSP) Read/Write 4-64 Registers DNAD DMA Next Address This 32-bit register contains the general purpose address pointer. At the start of some SCRIPTS operations, its value is copied from the (DSPS) register.
Page 157 Registers: 0x30–0x33 DMA SCRIPTS Pointer Save (DSPS) Read/Write DSPS Registers: 0x34–0x37 Scratch Register A (SCRATCHA) Read/Write SCRATCHA SCSI Registers DSPS DMA SCRIPTS Pointer Save This register contains the second Dword of a SCRIPTS instruction. It is overwritten each time a SCRIPTS instruction is fetched.
Page 158 (REQ/) is also asserted during start-of-transfer and end-of-transfer cleanup and alignment, even if less than a full burst of transfers is performed. The LSI53C875A inserts a “fairness delay” of four CLKs between burst transfers (as set in BL[2:0]) during normal operation. The fairness delay is not inserted during PCI retry cycles.
Page 159 I/O space; and if cleared, then the source address is in memory space. This function is useful for register-to-memory operations using the Memory Move instruction when the LSI53C875A is I/O mapped. Bits 4 and 5 of the Two (CTEST2) configuration status of the LSI53C875A. DIOM...
Page 160 Multiple command is used on all read cycles when it is legal. Burst Opcode Fetch Enable Setting this bit causes the LSI53C875A to fetch instructions in burst mode. Specifically, the chip bursts in the first two Dwords of all instructions using a single bus ownership.
Page 161 Register: 0x39 DMA Interrupt Enable (DIEN) Read/Write MDPE Reserved MDPE Master Data Parity Error Bus Fault ABRT Aborted Single Step Interrupt SCRIPTS Interrupt Instruction Received Reserved Illegal Instruction Detected This register contains the interrupt mask bits corresponding to the interrupting conditions described in the interrupt is masked by clearing the appropriate mask bit.
Page 162 This register is called the DMA Watchdog Timer on previous LSI53C8XX family products. PFEN IRQM Cache Line Size Enable Setting this bit enables the LSI53C875A to sense and react to cache line boundaries set up by the (DMODE) or PCI Cache Line Size contains the smaller value.
Page 163 LSI53C875A to make more efficient use of the system PCI bus, thus improving overall system performance. The unit will flush whenever the PFF bit is set, as well as on all transfer control instructions when the transfer conditions are met, on every write to the DMA SCRIPTS Pointer instruction, and when any interrupt is generated.
Page 164 The LSI53C875A fetches a SCSI SCRIPTS instruction from the address contained in the (DSP) register when this bit is set. This bit is required if the LSI53C875A is in one of the following modes: Manual start mode – Bit 0 in the (DMODE) register is set Single step mode –...
Page 165 Registers: 0x3C–0x3F Adder Sum Output (ADDER) Read Only ADDER Register: 0x40 SCSI Interrupt Enable Zero (SIEN0) Read/Write This register contains the interrupt mask bits corresponding to the interrupting conditions described in the (SIST0) bit. For more information on interrupts, see Description.”...
Page 166 Function Complete Indicates full arbitration and selection sequence is completed. Selected Indicates the LSI53C875A is selected by a SCSI initiator device. Set the Enable Response to Selection bit in the SCSI Chip ID (SCID) register for this to occur. Reselected Indicates the LSI53C875A is reselected by a SCSI target device.
Page 167 SCSI Reset Condition Indicates assertion of the SRST/ signal by the LSI53C875A or any other SCSI device. This condition is edge-triggered, so multiple interrupts cannot occur because of a single SRST/ pulse. SCSI Parity Error Indicates detection by the LSI53C875A of a parity error while receiving or sending SCSI data.
Page 168 Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending (the LSI53C875A stacks interrupts). SCSI interrupt conditions are individually masked through the...
Page 169 This bit is set when an arbitration only or full arbitration sequence is completed. Selected This bit is set when the LSI53C875A is selected by another SCSI device. The Enable Response to Selection bit must be set in the Response ID Zero (RESPID0) (RESPID1) LSI53C875A to respond to selection attempts.
Page 170 FIFO. Unexpected Disconnect This bit is set when the LSI53C875A is operating in the initiator mode and the target device unexpectedly disconnects from the SCSI bus. This bit is only valid when the LSI53C875A operates in the initiator mode.
Page 171 Reading the SIST1 clears the interrupt condition. Reserved Selection or Reselection Time-out The SCSI device which the LSI53C875A is attempting to select or reselect does not respond within the programmed time-out period. See the description of the SCSI Timer Zero (STIME0) information on the time-out timer.
Page 172 Data Bytes – 1. 11001100 2. 01010101 3. 00001111 4. 10010110 Note: 4-80 Registers check byte are received from the SCSI bus (all signals are shown active HIGH): Running SLPAR 00000000 11001100 (XOR of word 1) 10011001 (XOR of word 1 and 2) 10010110 (XOR of word 1, 2 and 3) Even Parity 00000000 A one in any bit position of the final SLPAR value would...
Page 173 Which byte is accessed is controlled by the SLPHBEN bit in the SCSI Control Two (SCNTL2) Register: 0x45 SCSI Wide Residue (SWIDE) Read/Write SWIDE SCSI Wide Residue After a wide SCSI data receive operation, this register contains a residual data byte if the last byte received was never sent across the DMA bus.
Page 174 PSCPT SCPTS Register: 0x47 General Purpose Pin Control Zero (GPCNTL0) Read/Write This register is used to determine if the pins controlled by the Purpose (GPREG0) correspond to bits [4:0] in the GPREG0 register. When the bits are enabled as inputs, internal pull-downs are enabled for GPIO[4:2] and internal pull-ups are enabled for GPIO[1:0].
Page 175 6 of GPCNTL0 is cleared and the chip is not in progress of performing an EEPROM autodownload regardless of the state of bit 0 (GPIO0). This provides a hardware solution to driving a SCSI activity LED in many implementations of LSI Logic SCSI chips. GPIO GPIO Enable General purpose control, corresponding to bits [4:2] in the GPREG0 register and pins GPIO[4:2].
Page 176 HTH [3:0] SEL [3:0] GEN [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1. These values are correct if the CCF bits in the register are set according to the valid combinations in the bit description. SEL[3:0] 4-84 Registers...
Page 177 Register: 0x49 SCSI Timer One (STIME1) Read/Write HTHBA GENSF Reserved HTHBA Handshake-to-Handshake Timer Bus Activity Enable Setting this bit causes this timer to begin testing for SCSI REQ/, ACK/ activity as soon as SBSY/ is asserted, regardless of the agents participating in the transfer. GENSF General Purpose Timer Scale Factor Setting this bit causes this timer to shift by a factor of 16.
Page 178 Register: 0x4A Response ID Zero (RESPID0) Read/Write RESPIO0 Register: 0x4B Response ID One (RESPID1) Read/Write RESPID1 4-86 Registers RESPID0 Response ID Zero RESPID0 and Response ID One (RESPID1) selection or reselection IDs. In other words, these two 8-bit registers contain the ID that the chip responds to on the SCSI bus.
Page 179 LSI53C875A can respond to. During a SCSI selection phase, when a valid ID is put on the bus, and the LSI53C875A responds to that ID, the ID that the chip was selected as will be written into the SSAID[3:0] bits.
Page 180 It is used in low level synchronous SCSI operations. When this bit is set, the LSI53C875A, as a target, is waiting for the initiator to acknowledge the data transfers. If the LSI53C875A is an initiator, then the target has sent the offset number of requests.
Page 181 Setting this bit allows assertion of all SCSI control and data lines through the SCSI Output Data Latch (SODL) of whether the LSI53C875A is configured as a target or initiator. Note: Do not set this bit during normal operation, since it could cause contention on the SCSI bus.
Page 182 SCSI Low level Mode Setting this bit places the LSI53C875A in the low level mode. In this mode, no DMA operations occur, and no SCRIPTS execute. Arbitration and selection may be...
Page 183 SCSI Request, Acknowledge, Data, and Parity signals to be actively deasserted, instead of relying on external pull-ups, when the LSI53C875A is driving these signals. Active deassertion of these signals occurs only when the LSI53C875A is in an information transfer phase.
Page 184 I mode. Disable Single Initiator Response If this bit is set, the LSI53C875A ignores all bus-initiated selection attempts that employ the single initiator option from SCSI-1. In order to select the LSI53C875A while this bit is set, the LSI53C875A’s SCSI ID and the initiator’s...
Page 185 SCSI bus can be read from this register. Data can be written to the Latch (SODL) LSI53C875A by reading this register to allow loopback testing. When receiving SCSI data, the data flows into this register and out to the host FIFO. This register differs...
Page 186 Frequency Lock This bit is used when enabling the SCSI clock quadrupler, which allows the LSI53C875A to transfer data at Ultra SCSI rates. Poll this bit for a 1 to determine that the clock quadrupler has locked. For more information on enabling...
Page 187 WSR bit is cleared and Phase Mismatch Jump Address 2 (PMJAD2) WSR bit is set. When this bit is set the LSI53C875A will use jump address one (PMJAD1) on data out (data out, command, message out) transfers and jump address two (PMJAD2) on data in (data in, status, message in) transfers.
Page 188 ENNDJ DISFC DILS 4-96 Registers Enable Jump on Nondata Phase Mismatches This bit controls whether or not a jump is taken during a nondata phase mismatch (i.e. message in, message out, status, or command). When this bit is clear, jumps will only be taken on Data-In or Data-Out phases and a phase mismatch interrupt will be generated for all other phases.
Page 189 LSI53C875A signals in the “AND-tree” test mode. In order to read data out of the LSI53C875A, this bit must be cleared. This bit is intended for board-level testing only. Do not set this bit during normal system operation.
Page 190 EN64TIBMV EN64DBMV Registers: 0x58–0x59 SCSI Bus Data Lines (SBDL) Read Only SBDL 4-98 Registers Index Mode 1 (64TIMOD set) table entry format: [31:24] Src/Dest Addr [39:32] Source/Destination Address [31:0] Enable 64-Bit Table Indirect BMOV Setting this bit enables 64-bit addressing for Table Indirect BMOVs using the upper byte (bit [24:31]) of the first Dword of the table entry.
Page 191: 64-Bit Scripts Selectors
Register: 0x5A–0x5B Reserved Registers: 0x5C–0x5F Scratch Register B (SCRATCHB) Read/Write SCRATCHB Registers: 0x60–0x9F Scratch Registers C–R (SCRATCHC–SCRATCHR) Read/Write These are general purpose user definable scratch pad registers. Apart from CPU access, only register read/write, memory moves and Load and Stores directed at a SCRATCH register will alter its contents. The power-up values are indeterminate.
Page 192 A special mode of this register can be enabled by setting the PCI Configuration Enable bit in the (CTEST2) register. Because the LSI53C875A supports only a 32-bit memory mapped PCI base address, the MMRS register is always read as 0x00000000 when in the special mode.
Page 193 A special mode of this register can be enabled by setting the PCI Configuration Into Enable bit in the (CTEST2) register. Because the LSI53C875A supports only a 32-bit SCRIPTS RAM PCI base address, the MMWS register is always read as 0x00000000 when in the special mode.
Page 194 Registers: 0xAC–0xAF DSA Relative Selector (DRS) Read/Write Registers: 0xB0–0xB3 Static Block Move Selector (SBMS) Read/Write SBMS 4-102 Registers Writes to the SFS register are unaffected. Clearing the PCI Configuration Into Enable bit causes the SFS register to return to normal operation. DSA Relative Selector Supplies the upper Dword of a 64-bit address during table indirect fetches and Load and Store...
Page 195: Phase Mismatch Jump Registers
Registers: 0xB4–0xB7 Dynamic Block Move Selector (DBMS) Read/Write DBMS Registers: 0xB8–0xBB DMA Next Address 64 (DNAD64) Read/Write DNAD64 Registers: 0xBC–0xBF Reserved 4.4 Phase Mismatch Jump Registers Eight 32-bit registers contain the byte count and addressing information required to update the direct, indirect, or table indirect BMOV instructions with new byte counts and addresses.
Page 196 Registers: 0xC0–0xC3 Phase Mismatch Jump Address 1 (PMJAD1) Read/Write PMJAD1 Registers: 0xC4–0xC7 Phase Mismatch Jump Address 2 (PMJAD2) Read/Write PMJAD2 4-104 Registers PMJAD1 Phase Mismatch Jump Address 1 This register contains the 32-bit address that will be jumped to upon a phase mismatch. Depending upon the state of the PMJCTL bit in register (CCNTL0) this address will either be used during an...
Page 197 Registers: 0xC8–0xCB Remaining Byte Count (RBC) Read/Write Registers: 0xCC–0xCF Updated Address (UA) Read/Write Phase Mismatch Jump Registers Remaining Byte Count (RBC) This register contains the byte count that remains for the BMOV that was executing when the phase mismatch occurred. In the case of direct or indirect BMOV instructions, the upper byte of this register will also contain the opcode of the BMOV that was executing.
Page 198 Registers: 0xD0–0xD3 Entry Storage Address (ESA) Read/Write This register's value depends on the type of BMOV being executed. The three types of BMOVs are listed below. Direct BMOV: Indirect BMOV: Table Indirect BMOV: 4-106 Registers In the case of a SCSI data receive, if there is a byte in SCSI Wide Residue (SWIDE) address will point to the location where that byte must be stored.
Page 199 Registers: 0xD4–0xD7 Instruction Address (IA) Read/Write Registers: 0xD8–0xDA SCSI Byte Count (SBC) Read Only Phase Mismatch Jump Registers Instruction Address This register always contains the address of the BMOV instruction that was executing when the phase mismatch occurred. This value will always match the value in the Entry Storage Address (ESA) table indirect BMOV in which case the ESA will have the address of the table indirect entry and this register will...
Page 200 Register: 0xDB Reserved Registers: 0xDC–0xDF Cumulative SCSI Byte Count (CSBC) Read/Write CSBC Registers: 0xE0–0xFF Reserved 4-108 Registers cannot be counted for this BMOV as it was actually part of the byte count for the previous BMOV. CSBC Cumulative SCSI Byte Count This loadable register contains a cumulative count of the actual number of bytes that have been transferred across the SCSI bus during data phases, i.e.
Page 201: Chapter 5 Scsi Scripts Instruction Set
Section 5.6, “Transfer Control Instructions” Section 5.7, “Memory Move Instructions” Section 5.8, “Load and Store Instructions” After power-up and initialization, the LSI53C875A can be operated in the low level register interface mode or in the high level SCSI SCRIPTS mode.
Page 202: High Level Scsi Scripts Mode
5.2 High Level SCSI SCRIPTS Mode To operate in the SCSI SCRIPTS mode, the LSI53C875A requires only a SCRIPTS start address. The start address must be at a Dword (four byte) boundary.
Page 203: Sample Operation
SCSI SCRIPTS program for execution. Loading the LSI53C875A to fetch its first instruction at the address just loaded. This is from main memory or the internal RAM, depending on the address. High Level SCSI SCRIPTS Mode...
Page 204 LSI53C875A requests use of the PCI bus again to transfer the data. When the LSI53C875A is granted the PCI bus, it executes (as a bus master) a burst transfer (programmable size) of data, decrement the internally stored remaining byte count, increment the address pointer, and then release the PCI bus.
Page 205: Scripts Overview
Data Structure Message Buffer Command Buffer Data Buffer Status Buffer High Level SCSI SCRIPTS Mode Write DSA Write Fetch SCRIPTS LSI53C875A SCSI Bus For details, see block diagram in Chapter 2 Data...
Page 206: Block Move Instruction
5.3 Block Move Instruction Performing a Block Move instruction, bit 5, Source I/O - Memory Enable (SIOM) and bit 4, Destination I/O - Memory Enable (DIOM) in the Mode (DMODE) address resides in memory or I/O space. When data is being moved onto the SCSI bus, SIOM controls whether that data comes from I/O or memory space.
Page 207 Direct Addressing The byte count and absolute address are: Command Indirect Addressing Use the fetched byte count, but fetch the data address from the address in the instruction. Command Once the data pointer address is loaded, it is executed as when the chip operates in the direct mode. This indirect feature allows a table of data buffer addresses to be specified.
Page 208 For a MOVE instruction, the 24-bit byte count is fetched from system memory. Then the 32-bit physical address is brought into the LSI53C875A. Execution of the move begins at this point. SCRIPTS can directly execute operating system I/O data structures, saving time at the beginning of an I/O operation.
Page 209 MOVE/MOVE64 CHMOV/CHMOV64 These instructions perform the following steps: 1. The LSI53C875A verifies that it is connected to the SCSI bus as a Target before executing this instruction. 2. The LSI53C875A asserts the SCSI phase signals (SMSG/, SC_D/, and SI_O/) as defined by the Phase Field bits in the instruction.
Page 210 CHMOV MOVE These instructions perform the following steps: 1. The LSI53C875A verifies that it is connected to the SCSI bus as an Initiator before executing this instruction. 2. The LSI53C875A waits for an unserviced phase to occur. An unserviced phase is any phase (with SREQ/ asserted) for which the LSI53C875A has not yet transferred data by responding with a SACK/.
Page 211 Set ATN instruction), the LSI53C875A deasserts SATN/ during the final SREQ/SACK/ handshake. 7. When the LSI53C875A is performing a block move for Message-In phase, it does not deassert the SACK/ signal for the last SREQ/SACK/ handshake. Clear the SACK/ signal using the Clear SACK I/O instruction.
Page 212: Scsi Information Transfer Phase
Message-Out Message-In Transfer Counter This 24-bit field specifies the number of data bytes to be moved between the LSI53C875A and system memory. The field is stored in the DMA Byte Counter (DBC) register. When the LSI53C875A transfers data to/from memory, the DBC register is decremented by the number of bytes transferred.
Page 213: Second Dword
The table entry contains byte count and address information. register. OPC1 OPC0 Target Mode Reselect Disconnect Wait Select Clear Register register. When the LSI53C875A Data Structure Address Initiator Mode Select Wait Disconnect Wait Reselect Clear [31:0] (DSA). 5-13...
Page 214: First Dword
Target mode operations. Target Mode OPC2 OPC1 OPC0 Reselect Instruction The LSI53C875A arbitrates for the SCSI bus by asserting the SCSI ID stored in the If it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status.
Page 215 32-bit jump address field stored in the DMA Next Address (DNAD) the LSI53C875A to Initiator mode if it is reselected, or to Target mode if it is selected. Disconnect Instruction The LSI53C875A disconnects from the SCSI bus by deasserting all SCSI signal outputs.
Page 216 Wait Disconnect Wait Reselect Clear Select Instruction The LSI53C875A arbitrates for the SCSI bus by asserting the SCSI ID stored in the If it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status.
Page 217 LSI53C875A to Initiator mode if it is reselected, or to Target mode if it is selected. If the Select with SATN/ field is set, the SATN/ signal is asserted during the selection phase. Wait Disconnect Instruction The LSI53C875A waits for the Target to perform a “legal”...
Page 218 5-18 SCSI SCRIPTS Instruction Set Relative Addressing Mode When this bit is set, the 24-bit signed value in the Next Address (DNAD) register is used as a relative displacement from the current DMA SCRIPTS Pointer (DSP) address. Use this bit only in conjunction with the Select, Reselect, Wait Select, and Wait Reselect instructions.
Page 219 Use this bit only in conjunction with the Select, Reselect, Wait Select, and Wait Reselect instructions. Use bits 25 and 26 individually or in = combination to produce the following conditions: Direct Table Indirect Relative Table Relative Direct Uses the device ID and physical address in the instruction.
Page 220 Set/Clear Target Mode This bit is used in conjunction with a Set or Clear instruction to set or clear Target mode. Setting this bit with a Set instruction configures the LSI53C875A as a Target device (this sets bit 0 of the (SCNTL0) register).
Page 221: Second Dword
Since SACK/ and SATN/ are Initiator signals, they are not asserted on the SCSI bus unless the LSI53C875A is operating as an Initiator or the SCSI Loopback Enable bit is set in the...
Page 222: Read/Write Instructions
5.5 Read/Write Instructions The Read/Write instruction supports addition, subtraction, and comparison of two separate values within the chip. It performs the desired operation on the specified register and the Received (SFBR) register or the SFBR. If the COM bit DMA Control (DCNTL bit 0) is cleared, Read/Write instructions cannot be used.
Page 223: Second Dword
It is possible to change register values from SCRIPTS in read-modify-write cycles or move to/from SFBR cycles. A[6:0] selects an 8-bit source/destination register within the LSI53C875A. Immediate Data This 8-bit value is used as a second operand in logical and arithmetic functions.
Page 224: Read/Write Instructions
5.5.4 Move To/From SFBR Cycles All operations are read-modify-writes. However, two registers are involved, one of which is always the SFBR. read-modify-write operations. The possible functions of this instruction are: Write one byte (value contained within the SCRIPTS instruction) into any chip register.
Page 225: Transfer Control Instructions
Table 5.3 Read/Write Instructions (Cont.) OpCode 111 Operator Read-Modify-Write AND data with register and place the result in the same register. Syntax: “Move RegA & data8 to RegA” Shift register one bit to the right and place the result in the same register.
Page 226: Transfer Control Instructions
Transfer Control Instructions OPC2 OPC1 Jump Instruction The LSI53C875A can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as defined by the Phase Compare, Data Compare and True/False bit fields. If the comparisons are true, then it loads the...
Page 227 DMA SCRIPTS Pointer Save (DSPS) register now contains the address of the next instruction. If the comparisons are false, the LSI53C875A fetches the next instruction from the address pointed to by the SCRIPTS Pointer (DSP) pointer unchanged. Call Instruction The LSI53C875A can do a true/false comparison of the...
Page 228 SCSIP[2:0] 5-28 SCSI SCRIPTS Instruction Set If the comparisons are false, the LSI53C875A fetches the next instruction from the address pointed to by the DSP register and the instruction pointer is not modified. Interrupt Instruction The LSI53C875A can do a true/false comparison of the...
Page 229: Scsi Phase Comparisons
The SCRIPTS program counter is a 32-bit value pointing to the SCRIPTS currently under execution by the LSI53C875A. The next address is formed by adding the 32-bit program counter to the 24-bit signed value of the last 24 bits of the Jump or Call instruction. Because it is...
Page 230 (Interrupt Status One (ISTAT1) bit 2) is asserted. Jump If True/False This bit determines whether the LSI53C875A branches when a comparison is true or when a comparison is false. This bit applies to phase compares, data compares, and carry tests. If both the Phase Compare and Data Compare bits are set, then both compares must be true to branch on a true condition.
Page 231 SCSI SATN/ signal. Wait for Valid Phase If the Wait for Valid Phase bit is set, the LSI53C875A waits for a previously unserviced phase before comparing the SCSI phase and data.
Page 232: Second Dword
The Memory Move instruction is used to copy the specified number of bytes from the source address to the destination address. Allowing the LSI53C875A to perform memory moves frees the system processor for other tasks and moves data at higher speeds than available from current DMA controllers.
Page 233: First Dword
These bits are reserved and must be zero. If any of these bits are set, an illegal instruction interrupt occurs. No Flush When this bit is set, the LSI53C875A performs a Memory Move without flushing the prefetch unit. When this bit is cleared, the Memory Move instruction automatically flushes the prefetch unit.
Page 234: Read/Write System Memory From Scripts
By using the Memory Move instruction, single or multiple register values are transferred to or from system memory. Because the LSI53C875A responds to addresses as defined in the Address Register Zero (I/O) registers, it can be accessed during a Memory Move operation if the source or destination address decodes to within the chip’s register space.
Page 235: Third Dword
5.7.4 Third Dword 5.8 Load and Store Instructions The Load and Store instructions provide a more efficient way to move data from/to memory to/from an internal register in the chip without using the normal memory move instruction. The Load and Store instructions are represented by two Dword opcodes. The first Dword contains the Counter (DBC) SCRIPTS Pointer Save (DSPS)
Page 236: First Dword
Data Structure Address Reserved No Flush (Store instruction only) When this bit is set, the LSI53C875A performs a Store without flushing the prefetch unit. When this bit is cleared, the Store instruction automatically flushes the prefetch unit. Use No Flush if the source and destination are not within four instructions of the current Store instruction.
Page 237: Second Dword
Store. Reserved Register Address A[6:0] selects the register to Load and Store to/from within the LSI53C875A. Reserved Byte Count This value is the number of bytes to Load and Store. Register - Memory I/O Address/DSA Offset...
Page 238 5-38 SCSI SCRIPTS Instruction Set...
Page 239: Chapter 6 Electrical Specifications
Section 6.4, “PCI and External Memory Interface Timing Diagrams” Section 6.5, “SCSI Timing Diagrams” Section 6.6, “Package Diagrams” 6.1 DC Characteristics This section of the manual describes the LSI53C875A DC characteristics. specifications. LSI53C875A PCI to Ultra SCSI Controller Table 6.1 through Table 6.10...
Page 240: Absolute Maximum Stress Ratings
Table 6.1 Absolute Maximum Stress Ratings Symbol Parameter Storage temperature Supply voltage Input voltage Latch-up current Electrostatic discharge 1. Stresses beyond those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the Operating Conditions 2 V <...
Page 241: Bidirectional Signals—Gpio0_Fetch/, Gpio1_Master Gpio[2:4]
Table 6.4 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/, MWE/ Symbol Parameter Input high voltage Input low voltage Output high voltage Output low voltage 3-state leakage Pull-down current PULL Table 6.5 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO[2:4] Symbol Parameter Input high voltage Input low voltage Output high voltage Output low voltage 3-state leakage...
Page 242: Bidirectional Signals—Ad[31:0], C_Be[3:0]/, Frame Irdy/, Trdy/, Devsel/, Stop/, Perr/, Par
Table 6.6 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR Symbol Parameter Input high voltage Input low voltage Output high voltage Output low voltage 3-state leakage Pull-down current PULL Table 6.7 Input Signals—CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI, TEST_HSC, TEST_RST, TMS, TRST/ Symbol Parameter Input high voltage...
Page 243: Output Signals—Irq/, Mac/_Testout, Req/
Output low voltage 3-state leakage 6.2 TolerANT Technology Electrical Characteristics The LSI53C875A features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers. Active negation actively drives the SCSI Request, Acknowledge, Data, and Parity signals HIGH rather than allowing them to be passively pulled up by terminators.
Page 244: Tolerant Technology Electrical Characteristics For Se Scsi Signals
Table 6.11 TolerANT Technology Electrical Characteristics for SE SCSI Signals Symbol Parameter Output high voltage Output low voltage Input high voltage Input low voltage Input clamp voltage Threshold, HIGH to LOW Threshold, LOW to HIGH –V Hysteresis Output high current Output low current Short-circuit output high current Short-circuit output low current...
Page 245: Rise And Fall Time Test Condition
Figure 6.1 Figure 6.2 SCSI Input Filtering REQ/ or SACK/ Input Note: t is the input filtering period. Figure 6.3 TolerANT Technology Electrical Characteristics Rise and Fall Time Test Condition 20 pF 2.5 V Hysteresis of SCSI Receivers Input Voltage (Volts)
Page 246: Output Current As A Function Of Output Voltage
Figure 6.4 Figure 6.5 Output Current as a Function of Output Voltage Output Voltage (Volts) Electrical Specifications Input Current as a Function of Input Voltage 8.2 V 0.7 V OUTPUT ACTIVE Input Voltage (Volts) 14.4 V HIGH-Z Output Voltage (Volts)
Page 247: Ac Characteristics
6.3 AC Characteristics The AC characteristics described in this section apply over the entire range of operating conditions (refer to the Chip timings are based on simulation at worst case voltage, temperature, and processing. Timing was developed with a load capacitance of 50 pF. Table 6.12 Table 6.12 External Clock...
Page 248: Interrupt Output
Table 6.13 Table 6.13 Reset Input Symbol Parameter Reset pulse width Reset deasserted setup to CLK HIGH MAD setup time to CLK HIGH (for configuring the MAD bus only) MAD hold time from CLK HIGH (for configuring the MAD bus only) Figure 6.7 Reset Input RST/...
Page 249: Pci And External Memory Interface Timing Diagrams
IRQ/ 6.4 PCI and External Memory Interface Timing Diagrams Figure 6.9 LSI53C875A accesses the PCI bus. This section includes timing diagrams for access to three groups of memory configurations. The first group applies to Timing. The third group applies to...
Page 250 – – – – External Memory Timing – – – – – – – – – – 6-12 Electrical Specifications Burst Read, 32-Bit Address and Data Burst Read, 64-Bit Address and Data Burst Write, 32-Bit Address and Data Burst Write, 64-Bit Address and 32-Bit Data External Memory Read External Memory Write Normal/Fast Memory ( 128 Kbytes) Single Byte Access Read...
Page 251: Target Timing
(Driven by Master-Addr; LSI53C875A-Data) C_BE/ (Driven by Master (Driven by Master-Addr; LSI53C875A-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) IDSEL (Driven by Master) PCI and External Memory Interface Timing Diagrams Addr Byte Enable –...
Page 252: Pci Configuration Register Write
(Driven by System) FRAME/ (Driven by Master) (Driven by Master) C_BE/ (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) IDSEL (Driven by Master) 6-14 Electrical Specifications Addr...
Page 253: Bit Operating Register/Scripts Ram Read
(Driven by Master-Addr; LSI53C875A-Data) C_BE/ (Driven by Master) (Driven by Master-Addr; LSI53C875A-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) PCI and External Memory Interface Timing Diagrams Byte Enable – – –...
Page 254: Bit Address Operating Register/Scripts Ram Read
Addr (Driven by Master-Addr; LSI53C875A-Data) C_BE[3:0] Dual (Driven by Master) Addr (Driven by Master-Addr; LSI53C875A-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) 6-16 Electrical Specifications Addr Byte Enable Unit – –...
Page 255: Bit Operating Register/Scripts Ram Write
(Driven by Master) Addr (Driven by Master) C_BE/ (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) PCI and External Memory Interface Timing Diagrams Unit – –...
Page 256: Bit Address Operating Register/Scripts Ram Write
(Driven by System) FRAME/ (Driven by Master) (Driven by Master) C_BE/ (Driven by Master) (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) 6-18 Electrical Specifications Addr Addr Data In...
Page 257: Initiator Timing
6.4.2 Initiator Timing The tables and figures in this section describe LSI53C875A initiator timings. Table 6.21 Nonburst Opcode Fetch, 32-Bit Address and Data Symbol Parameter Shared signal input setup time Shared signal input hold time CLK to shared signal output valid...
Page 258: Nonburst Opcode Fetch, 32-Bit Address And Data
Figure 6.15 Nonburst Opcode Fetch, 32-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C875A) GPIO1_MASTER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C875A) (Driven by LSI53C875A- Addr; Target-Data) C_BE/ (Driven by LSI53C875A)
Page 259: Burst Opcode Fetch, 32-Bit Address And Data
Table 6.22 Burst Opcode Fetch, 32-Bit Address and Data Symbol Parameter Shared signal input setup time Shared signal input hold time CLK to shared signal output valid Side signal input setup time Side signal input hold time CLK to side signal output valid CLK HIGH to GPIO0_FETCH/ LOW CLK HIGH to GPIO0_FETCH/ HIGH CLK HIGH to GPIO1_MASTER/ LOW...
Page 260: Burst Opcode Fetch, 32-Bit Address And Data
Figure 6.16 Burst Opcode Fetch, 32-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C875A) GPIO1_MASTER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C875A) (Driven by LSI53C875A- Addr; Target-Data) C_BE/ (Driven by LSI53C875A)
Page 261: Back-To-Back Read, 32-Bit Address And Data
Table 6.23 Back-to-Back Read, 32-Bit Address and Data Symbol Parameter Shared signal input setup time Shared signal input hold time CLK to shared signal output valid Side signal input setup time Side signal input hold time CLK to side signal output valid CLK HIGH to GPIO1_MASTER/ LOW CLK HIGH to GPIO1_MASTER/ HIGH PCI and External Memory Interface Timing Diagrams...
Page 262: Back-To-Back Read, 32-Bit Address And Data
Figure 6.17 Back-to-Back Read, 32-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C875A GPIO1_MASTER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C875A) (Driven by LSI53C875A- Addr; Target-Data) C_BE/ (Driven by LSI53C875A) (Driven by LSI53C875A- Addr;...
Page 263: Back-To-Back Write, 32-Bit Address And Data
Table 6.24 Back-to-Back Write, 32-Bit Address and Data Symbol Parameter Shared signal input setup time Shared signal input hold time CLK to shared signal output valid Side signal input setup time Side signal input hold time CLK to side signal output valid CLK HIGH to GPIO1_MASTER/ LOW CLK HIGH to GPIO1_MASTER/ HIGH PCI and External Memory Interface Timing Diagrams...
Page 264: Back-To-Back Write, 32-Bit Address And Data
Figure 6.18 Back-to-Back Write, 32-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C875A) GPIO1_MASTER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C875A) (Driven by LSI53C875A- Addr; Target-Data) C_BE/ (Driven by LSI53C875A) (Driven by LSI53C875A- Addr;...
Page 265: Burst Read, 32-Bit Address And Data
Table 6.25 Burst Read, 32-Bit Address and Data Symbol Parameter Shared signal input setup time Shared signal input hold time CLK to shared signal output valid PCI and External Memory Interface Timing Diagrams Unit – – 6-27...
Page 266: Burst Read, 32-Bit Address And Data
Figure 6.19 Burst Read, 32-Bit Address and Data GPIO0_FETCH/ (Driven by LSI53C875A) GPIO1_MASTER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C875A) (Driven by LSI53C875A- Addr; Target-Data) C_BE/ (Driven by LSI53C875A) (Driven by LSI53C875A- Addr;...
Page 267: Burst Read, 64-Bit Address And Data
Table 6.26 Burst Read, 64-Bit Address and Data Symbol Parameter Shared signal input setup time Shared signal input hold time CLK to shared signal output valid CLK HIGH to GPIO1_MASTER/HIGH PCI and External Memory Interface Timing Diagrams Unit – – –...
Page 268: Burst Read, 64-Bit Address And Data
(Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C875A) AD[31:0] (Addr driven by LSI53C875A- Data driven by Target) C_BE[3:0]/ (Driven by LSI53C875A) (Addr drvn by LSI53C875A; Data drvn by Target) IRDY/ (Driven by LSI53C875A)
Page 269: Burst Write, 32-Bit Address And Data
Table 6.27 Burst Write, 32-Bit Address and Data Symbol Parameter Shared signal input setup time Shared signal input hold time CLK to shared signal output valid CLK HIGH to GPIO1_MASTER/ HIGH PCI and External Memory Interface Timing Diagrams Unit – –...
Page 270: Burst Write, 32-Bit Address And Data
Figure 6.21 Burst Write, 32-Bit Address and Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C875A) GPIO1_MASTER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C875A) (Driven by LSI53C875A) C_BE/ (Driven by LSI53C875A) (Driven by LSI53C875A)
Page 271: Burst Write, 64-Bit Address And 32-Bit Data
Table 6.28 Burst Write, 64-Bit Address and 32-Bit Data Symbol Parameter Shared signal input setup time Shared signal input hold time CLK to shared signal output valid CLK HIGH to GPIO1_MASTER/ HIGH PCI and External Memory Interface Timing Diagrams Unit –...
Page 272: Burst Write, 64-Bit Address And 32-Bit Data
Figure 6.22 Burst Write, 64-Bit Address and 32-Bit Data (Driven by System) GPIO0_FETCH/ (Driven by LSI53C875A) GPIO1_MASTER/ (Driven by LSI53C875A) REQ/ (Driven by LSI53C875A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C875A) AD[31:0] (Driven by LSI53C875A) C_BE[3:0]/ (Driven by LSI53C875A)
Page 273: External Memory Timing
6.4.3 External Memory Timing The tables and figures in this section describe LSI53C875A external timings. The External Memory Write timings start on Table 6.29 External Memory Read Symbol Parameter Shared signal input setup time Shared signal input hold time CLK to shared signal output valid...
Page 274: External Memory Read
LSI53C875A-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) (Addr driven by LSI53C875A; Data driven by Memory) MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A) MCE/ (Driven by LSI53C875A) MOE/ (Driven by LSI53C875A)
Page 275 LSI53C875A-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) (Addr driven by LSI53C875A; Data driven by Memory) MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A) MCE/ (Driven by LSI53C875A) MOE/ (Driven by LSI53C875A)
Page 276: External Memory Write
Table 6.30 External Memory Write Symbol Parameter Shared signal input setup time Shared signal input hold time CLK to shared signal output valid Address setup to MAS/ HIGH Address hold from MAS/ HIGH MAS/ pulse width Data setup to MWE/ LOW Data hold from MWE/ HIGH MWE/ pulse width Address setup to MWE/ LOW...
Page 277 The External Memory Write timings start on page 6-40. PCI and External Memory Interface Timing Diagrams 6-39...
Page 278: External Memory Write
LSI53C875A-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) (Addr driven by LSI53C875A; Data driven by Memory) MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A) MCE/ (Driven by LSI53C875A) MOE/ (Driven by LSI53C875A)
Page 279 LSI53C875A-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) (Addr driven by LSI53C875A; Data driven by Memory) MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A) MCE/ (Driven by LSI53C875A) MOE/ (Driven by LSI53C875A)
Page 280: Normal/Fast Memory ( 128 Kbytes) Single Byte Access Read Cycle
Data hold from address, MOE/, MCE/ change Address out from MOE/, MCE/ HIGH Data setup to CLK HIGH Figure 6.25 Normal/Fast Memory ( = 128 Kbytes) Single Byte Access Read Cycle (Addr driven by LSI53C875A; Data driven by memory) MAS1/ (Driven by LSI53C875A)
Page 281: Normal/Fast Memory ( 128 Kbytes) Single Byte Access Write Cycle
Address setup to MWE/ LOW MCE/ LOW to MWE/ HIGH MCE/ LOW to MWE/ LOW MWE/ HIGH to MCE/ HIGH Figure 6.26 Normal/Fast Memory ( = 128 Kbytes) Single Byte Access Write Cycle (Driven by LSI53C875A) MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A)
Page 282: Normal/Fast Memory ( 128 Kbytes) Multiple Byte Access Read Cycle
Master-Addr; Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) (Addr Driven by LSI53C875A; Data driven by Memory) MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A) MCE/ (Driven by LSI53C875A) MOE/ (Driven by LSI53C875A)
Page 283 Master-Addr; Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) (Addr Driven by LSI53C875A Data driven by Memory) MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A) MCE/ (Driven by LSI53C875A) MOE/ (Driven by LSI53C875A)
Page 284: Normal/Fast Memory ( 128 Kbytes) Multiple Byte Access Write Cycle
Addr In (Driven by Master-Addr; LSI53C875A-Data) C_BE[3:0]/ (Driven by Master) (Driven by Master-Addr; LSI53C875A-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) (Driven by LSI53C875A) MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A)
Page 285 (Driven by Master) (Driven by Master-Addr; LSI53C875A-Data) C_BE[3:0]/ (Driven by Master) (Driven by Master-Addr; LSI53C875A-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C875A) STOP/ (Driven by LSI53C875A) DEVSEL/ (Driven by LSI53C875A) Data Out (Driven by LSI53C875A; MAS1/ (Driven by LSI53C875A) MAS0/...
Page 286: Slow Memory ( 128 Kbytes) Read Cycle
Data hold from address, MOE/, MCE/ change Address out from MOE/, MCE/ HIGH Data setup to CLK HIGH Figure 6.29 Slow Memory ( = 128 Kbytes) Read Cycle (Address driven by LSI53C875A; Data driven by Memory) MAS1/ (Driven by LSI53C875A)
Page 287: Slow Memory ( 128 Kbytes) Write Cycle
Address setup to MWE/ LOW MCE/ LOW to MWE/ HIGH MCE/ LOW to MWE/ LOW MWE/ HIGH to MCE/ HIGH Figure 6.30 Slow Memory ( = 128 Kbytes) Write Cycle (Driven by LSI53C875A) MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A)
Page 288: Kbytes Rom Read Cycle
Data hold from address, MOE/, MCE/ change Address out from MOE/, MCE/ HIGH Data setup to CLK HIGH Figure 6.31 64 Kbytes ROM Read Cycle (Address driven by LSI53C875A; Data driven by Memory) MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A)
Page 289: Kbyte Rom Write Cycle
Address setup to MWE/ LOW MCE/ LOW to MWE/ HIGH MCE/ LOW to MWE/ LOW MWE/ HIGH to MCE/ HIGH Figure 6.32 64 Kbyte ROM Write Cycle (Driven by LSI53C875A) MAS1/ (Driven by LSI53C875A) MAS0/ (Driven by LSI53C875A) MCE/ (Driven by LSI53C875A)
Page 290: Scsi Timing Diagrams
6.5 SCSI Timing Diagrams The tables and diagrams in this section describe the LSI53C875A SCSI timings. Table 6.37 Initiator Asynchronous Send Symbol Parameter SACK/ asserted from SREQ/ asserted SACK/ deasserted from SREQ/ deasserted Data setup to SACK/ asserted Data hold from SREQ/ deasserted Figure 6.33 Initiator Asynchronous Send...
Page 291: Initiator Asynchronous Receive
Table 6.38 Initiator Asynchronous Receive Symbol Parameter SACK/ asserted from SREQ/ asserted SACK/ deasserted from SREQ/ deasserted Data setup to SREQ/ asserted Data hold from SACK/ asserted Figure 6.34 Initiator Asynchronous Receive SREQ/ SACK/ SD[15:0]/, SDP[1:0]/ SCSI Timing Diagrams Valid n –...
Page 292: Target Asynchronous Send
Table 6.39 Target Asynchronous Send Symbol Parameter SREQ/ deasserted from SACK/ asserted SREQ/ asserted from SACK/ deasserted Data setup to SREQ/ asserted Data hold from SACK/ asserted Figure 6.35 Target Asynchronous Send SREQ/ SACK/ SD[15:0]/, Valid n SDP[1:0]/ 6-54 Electrical Specifications Unit –...
Page 293: Target Asynchronous Receive
Table 6.40 Target Asynchronous Receive Symbol Parameter SREQ/ deasserted from SACK/ asserted SREQ/ asserted from SACK/ deasserted Data setup to SACK/ asserted Data hold from SREQ/ deasserted Figure 6.36 Target Asynchronous Receive SREQ/ SACK/ SD[15:0]/, SDP[1:0]/ Table 6.41 SCSI-1 Transfers (5.0 Mbytes) Symbol Parameter Send SREQ/ or SACK/ assertion pulse width...
Page 294: Ultra Scsi Transfers 20.0 Mbytes (8-Bit Transfers) Or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 Mhz Clock
Table 6.42 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) 40 MHz Clock Symbol Parameter Send SREQ/ or SACK/ assertion pulse width Send SREQ/ or SACK/ deassertion pulse width Receive SREQ/ or SACK/ assertion pulse width Receive SREQ/ or SACK/ deassertion pulse width Send data setup to SREQ/ or SACK/ asserted Send data hold from SREQ/ or SACK/ asserted...
Page 295: Initiator And Target Synchronous Transfer
Figure 6.37 Initiator and Target Synchronous Transfer SREQ/ or SACK/ Send Data SD[15:0]/, SDP[1:0]/ Receive Data SD[15:0]/, SDP[1:0]/ SCSI Timing Diagrams Valid n Valid n n + 1 Valid n + 1 Valid n + 1 6-57...
Page 296: Package Diagrams
Figure 6.38 LSI53C875A 160-Pin PQFP Mechanical Drawing Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code P3. 6-58...
Page 297 Figure 6.38 160-pin PQFP (P3) Mechanical Drawing (Sheet 2 of 2) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code P3. Package Diagrams...
Page 298: Pqfp Pin List By Location
Table 6.44 160 PQFP Pin List by Location Signal Signal C_BE[3]/ PCI_AD[6] IDSEL VSSIO PCI_AD[23] PCI_AD[5] VSSIO PCI_AD[4] PCI_AD[22] VDDIO PCI_AD[21] PCI_AD[3] PCI_AD[20] PCI_AD[2] VDDIO VSSIO PCI_AD[19] PCI_AD[1] VSSIO PCI_AD[0] PCI_AD[18] VDDCORE PCI_AD[17] IRQ/ PCI_AD[16] GPIO[0] VSSIO GPIO[1] C_BEN[2] VSSCORE FRAME/ SCLK IRDY/...
Page 299: Pin Bga Mechanical Drawing
Figure 6.39 169-Pin BGA Mechanical Drawing Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code GV. Package Diagrams...
Page 300: Bga Pin List By Location
Table 6.45 169 BGA Pin List by Location Signal Signal C_BE[3]/ PCI_AD[20]D3 PCI_AD[24] PCI_AD[25] PCI_AD[27] VDDIO PCI_AD[29] GNT/ VDDCORE MCE/ VDDA MAS[0]/ VSSIO SD[12] VSSIO TEST_HSC/ SD[15] PCI_AD[16] PCI_AD[17] IDSEL PCI_AD[18] PCI_AD[19] PCI_AD[22] PCI_AD[28] REQ/ SERR/ PCI_AD[31] RST/ VDDIO MOE/ MAS[1]/ SD[14] SD[0]...
Page 301: A.1 Lsi53C875A Pci Register Map
Command Data Device ID Expansion ROM Base Address Header Type Interrupt Line Interrupt Pin Latency Timer Max_Lat Min_Gnt Next Item Pointer LSI53C875A PCI to Ultra SCSI Controller Address Read/Write Page 0x14–0x17 Read/Write 0x18–0x1B Read/Write 4-10 0x10–0x13 Read/Write 0x46 Read Only...
Page 302: A.2 Lsi53C875A Scsi Register Map
Table A.1 LSI53C875A PCI Register Map (Cont.) Register Name Power Management Capabilities (PMC) Power Management Control/Status (PMCSR) Reserved Reserved Revision ID (Rev ID) Status Subsystem ID Subsystem Vendor ID Vendor ID Table A.2 LSI53C875A SCSI Register Map Register Name Adder Sum Output (ADDER)
Page 303 Table A.2 LSI53C875A SCSI Register Map (Cont.) Register Name DMA Command (DCMD) DMA Control (DCNTL) DMA FIFO (DFIFO) DMA Interrupt Enable (DIEN) DMA Mode (DMODE) DMA Next Address (DNAD) DMA Next Address 64 (DNAD64) DMA SCRIPTS Pointer (DSP) DMA SCRIPTS Pointer Save (DSPS)
Page 304 Table A.2 LSI53C875A SCSI Register Map (Cont.) Register Name Remaining Byte Count (RBC) Reserved Reserved Reserved Reserved Reserved Response ID One (RESPID1) Response ID Zero (RESPID0) Scratch Byte Register (SBR) Scratch Register A (SCRATCHA) Scratch Register B (SCRATCHB) Scratch Registers C–R (SCRATCHC–SCRATCHR) 0x60–0x9F...
Page 305 Table A.2 LSI53C875A SCSI Register Map (Cont.) Register Name SCSI Interrupt Enable Zero (SIEN0) SCSI Interrupt Status One (SIST1) SCSI Interrupt Status Zero (SIST0) SCSI Longitudinal Parity (SLPAR) SCSI Output Control Latch (SOCL) SCSI Output Data Latch (SODL) SCSI Selector ID (SSID)
Page 306 Register Summary...
Page 307: B.1 16 Kbyte Interface With 200 Ns Memory
MCE/ MAD[7:0] LSI53C875A MAS0/ MAS1/ Note: MAD[3:1] pulled LOW internally. MAD bus sense logic enabled for 16 Kbyte of slow memory (200 ns devices @ 33 MHz). LSI53C875A PCI to Ultra SCSI Controller MAD0 4.7 K HCT374 HCT374 D[7:0] A[7:0]...
Page 308: B.2 64 Kbyte Interface With 150 Ns Memory
+ 12 V GPIO4 MWE/ MOE/ MCE/ MAD[7:0] LSI53C875A MAS0/ MAS1/ Note: MAD 3, 1, 0 pulled LOW internally. MAD bus sense logic enabled for 64 Kbyte of fast memory (150 ns devices @ 33 MHz). External Memory Interface Diagram Examples Optional - for Flash Memory only, not required for EEPROMS.
Page 309 MWE/ MOE/ MCE/ MAD[7:0] LSI53C875A MAS0/ MAS1/ Note: MAD[2:0] pulled LOW internally. MAD bus sense logic enabled for 128, 256, 512 Kbytes, or 1 Mbyte of fast memory (150 ns devices @ 33 MHz). The HCT374s may be replaced with HCT377s.
Page 310: B.4 512 Kbyte Interface With 150 Ns Memory
MWE/ MOE/ MAD[7:0] MAD3 MAD1 MAD3 LSI53C875A MAS0/ MAS1/ MAD[2:0] MCE/ Note: MAD2 pulled LOW internally. MAD bus sense logic enabled for 512 Kbytes of slow memory (150 ns devices, additional time required for HCT139 @ 33 MHz). The HCT374s may be replaced with HCT377s.
Page 311 4-77 (COM) 4-72 (CON) 4-24, 4-49 (CP) 4-13 (CSBC) 4-108 (CSF) 4-92 (CTEST0) 4-53 (CTEST1) 4-53 (CTEST2) 4-54 LSI53C875A PCI to Ultra SCSI Controller (CTEST3) 4-56 (CTEST4) 4-59 (CTEST5) 4-60 (CTEST6) 4-62 (D1S) 4-16 (D2S) 4-16 (DACK) 4-55 (DATA) 4-18...
Page 312 (ERBA) 4-12 (ERL) 4-67 (ERMP) 4-68 (ESA) 4-106 (EWS) 4-29 (EXC) 4-23 (EXT) 4-90 (FBL3) 4-59 (FE) 4-82 (FF[3:0]) 4-43 (FF4) 4-46 (FFL) 4-53 (FLF) 4-56 (FLSH) 4-51 (FM) 4-56 (FMT) 4-53 (GEN) 4-75, 4-79 (GEN[3:0]) 4-85 (GENSF) 4-85 (GPCNTL0) 4-82 (GPIO) 4-35...
Page 313 (SGE) 4-74, 4-77 (SI) 4-51 (SID) 4-11 (SIEN0) 4-73 (SIEN1) 4-75 (SIGP) 4-49, 4-54 (SIOM) 4-67 (SIP) 4-50 (SIR) 4-40 (SIST0) 4-76 (SIST1) 4-78 (SLB) 4-89 (SLPAR) 4-79 (SLPHBEN) 4-27 (SLPMD) 4-27 (SLT) 4-87 (SOCL) 4-37 (SODL) 4-94 (SOM) 4-88 (SOZ) 4-87 (SPL1)
Page 314 burst (Cont.) length (BL[1:0]) 4-66 length bit 2 (BL2) 4-61 opcode fetch enable (BOF) 4-68 size selection command and byte enables fault (BF) 4-40, 4-69 byte count 5-37 empty in DMA FIFO (FMT) 4-53 full in DMA FIFO (FFL) 4-53 offset counter (BO) 4-57 cache line size 2-7,...
Page 315 interrupt (Cont.) pending (DIP) 4-50 mode (DMODE) 4-66 SCRIPTS pointer (DSP) 4-64 pointer save (DSPS) 4-65 status (DSTAT) 4-39 DMA next address (DNAD) 4-64 address 64 (DNAD64) 4-103 DMODE register 2-22 relative 5-36 relative selector (DRS) 4-102 DSPS register 5-34 DSTAT 2-38, 2-42, 2-43 dual address cycles...
Page 316 (LT) LED_CNTL (LEDC) 4-83 load and store instructions 2-22, 5-37 prefetch unit and store instructions loopback enable 2-23 lost arbitration (LOA) 4-43 LSI53C700 compatibility (COM) 4-72 LSI53C875A new features MAC/_TESTOUT 3-11 2-49 bus programming 3-14 pins 2-49 MAD[0] 3-15 MAD[3:1]...
Page 317 Min_Gnt (MG) 4-14 MOE/ 3-11 move to/from SFBR cycles 5-24 multiple cache line transfers MWE/ 3-11 new capabilities (NC) new features in the LSI53C875A Next_Item_Ptr (NIP) 4-15 no connections 3-13 no download mode 2-51 no flush 5-33 store instruction only...
Page 318 reset input 6-10 SCSI offset (ROF) 4-89 response ID one (RESPID1) 4-86 response ID zero (RESPID0) 4-86 return instruction 5-27 revision ID (RID) flash and memory interface signals 2-49 RST/ SACK 2-42 SACK/ status (ACK) 4-39 SACs 2-19 SATN/ status (ATN) 4-39 SBSY/ status (BSY) 4-39...
Page 319 2-39 select 2-17 instruction 5-16 with ATN/ 5-20 with SATN/ on a start sequence (WATN) selected (SEL) 4-74, 4-77 selection or reselection time-out (STO) 4-75, selection response logic test (SLT) 4-87 selection time-out (SEL[3:0]) 4-84 semaphore (SEM) 4-49 serial EEPROM interface 2-50 SERR/...
Page 320 Ultra SCSI (Cont.) single-ended transfers 20.0 Mbytes (16-bit transfers) quadrupled 40 MHz clock 6-56 20.0 Mbytes (8-bit transfers) 40 MHz clock 6-56 synchronous data transfers 2-36 unexpected disconnect (UDC) 4-74, 4-78 updated address (UA) 4-105 upper register address line (A7) 5-23 use data8/SFBR 5-22...
Page 321: Customer Feedback
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Page 322 Reader’s Comments Fax your comments to: Please tell us how you rate this document: LSI53C875A PCI to Ultra SCSI Controller Technical Manual. Place a check mark in the appropriate blank for each category. Completeness of information Clarity of information Ease of finding information...
Page 323 U.S. Distributors by State A. E. Avnet Electronics Colorado http://www.hh.avnet.com Denver B. M. Bell Microproducts, A. E. Inc. (for HAB’s) B. M. http://www.bellmicro.com W. E. I. E. Insight Electronics Englewood http://www.insight-electronics.com I. E. W. E. Wyle Electronics Idaho Springs http://www.wyle.com B.
Page 324 U.S. Distributors by State (Continued) New York South Carolina Hauppauge A. E. I. E. Tel: 516.761.0960 W. E. Long Island South Dakota A. E. Tel: 516.434.7400 A. E. W. E. Tel: 800.861.9953 W. E. Rochester A. E. Tel: 716.475.9130 Tennessee I.
Page 325 Direct Sales Representatives by State (Component and HAB) E. A. Earle Associates Texas E. L. Electrodyne - UT Austin Group 2000 I. S. Infinity Sales, Inc. Arlington ION Associates, Inc. R. A. Rathsburg Associ- Houston ates, Inc. Synergy Associates, Utah Inc.
Page 326 Sales Offices and Design Resource Centers LSI Logic Corporation Fort Collins Corporate Headquarters 2001 Danfield Court Fort Collins, CO 80525 1551 McCarthy Blvd Tel: 970.223.5100 Milpitas CA 95035 Tel: 408.433.8000 Fax: 970.206.5549 Fax: 408.433.8989 Florida NORTH AMERICA Boca Raton 2255 Glades Road...
Page 327 Sales Offices and Design Resource Centers (Continued) Korea Seoul LSI Logic Corporation of Korea Ltd 10th Fl., Haesung 1 Bldg. 942, Daechi-dong, Kangnam-ku, Seoul, 135-283 Tel: 82.2.528.3400 Fax: 82.2.528.2250 The Netherlands Eindhoven LSI Logic Europe Ltd World Trade Center Eindhoven Building ‘Rijder’...
Page 328 12 Interface Business Park Bincknoll Lane Fax: 31.40.2.510255 Wootton Bassett, Swindon, Wiltshire SN4 8SY Switzerland Tel: 44.1793.849933 Brugg Fax: 44.1793.859555 LSI Logic Sulzer AG Mattenstrasse 6a CH 2555 Brugg Sales Offices with Tel: 41.32.3743232 Design Resource Centers Fax: 41.32.3743233 Taiwan Taipei...

LSI LSI53C875A Technical Manual

Table of Contents

Chapter 1 General Description

Chapter 2 Functional Description

Chapter 3 Signal Descriptions

Chapter 4 Registers

Chapter 5 SCSI SCRIPTS Instruction Set

Chapter 6 Electrical Specifications

Bidirectional Signals—Mad[7:0], Mas/[1:0], Mce/, Moe Mwe/

Appendix A Register Summary

Appendix B External Memory Interface Diagram Examples

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Summary of Contents for LSI LSI53C875A