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Table 3.9
Pin Assignments for SFF-8067 Mode (Cont.)
Pin/Ball
Signal Name
No.
PA0
112/F8
PA1
111/E11
PA2
109/E12
PA3
108/E13
PA4
107/F9
PA5
106/F10
PA6
104/F13
Tied to V
103/F12
DD
Tied to V
102/G9
DD
Tied to V
101/G10
DD
Tied to V
99/G13
DD
Tied to V
98/G12
DD
Tied to V
97/G11
DD
Tied to V
96/H9
DD
Tied to V
95/H13
DD
Tied to V
94/H12
DD
3-22
Description
This pin contains bit 0 of the
physical address of the enclosure.
This pin contains bit 1 of the
physical address of the enclosure.
This pin contains bit 2 of the
physical address of the enclosure.
This pin contains bit 3 of the
physical address of the enclosure.
This pin contains bit 4 of the
physical address of the enclosure.
This pin contains bit 5 of the
physical address of the enclosure.
This pin contains bit 6 of the
physical address of the enclosure.
Signal Descriptions
Port 1
Port 1
Port 1
Port 1
Port 1
Port 1
Port 1
–
N/A
–
N/A
–
N/A
–
N/A
–
N/A
–
N/A
–
N/A
–
N/A
–
N/A
Pad
8067 Port
Configuration
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
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