LSI LSIFC929 Technical Manual

Dual channel fibre channerl i/o processor

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Technical

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LSIFC929 Dual Channel

Fibre Channel I/O

Processor

Revision 2.0

A u g u s t 2 0 0 1

S14073

Table of Contents

Summary of Contents for LSI LSIFC929

Page 1 Technical Manual LSIFC929 Dual Channel Fibre Channel I/O Processor Revision 2.0 A u g u s t 2 0 0 1 ® S14073...
Page 2 Shielded cables for SCSI connection external to the cabinet are used in the compliance testing of this Product. LSI Logic is not responsible for any radio or television interference caused by unauthorized modiﬁcation of this equipment or the substitution or attachment of connecting cables and equipment other than those speciﬁed by LSI Logic.
Page 3 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.
Page 5 This document was prepared for logic designers and applications engineers and is intended to provide an overview of the LSI Logic LSIFC929 and to explain how to use the LSIFC929 in the initial stages of system design. This document assumes that you have some familiarity with microprocessors and related support devices.
Page 6 • Chapter 3, LSIFC929 Overview, provides an introduction to the basic features of the LSIFC929, including the host interface, protocol assist engines, and support components. • Chapter 4, Signal Descriptions, lists and describes the signals on the LSIFC929. • Chapter 5, Register Descriptions, brieﬂy describes the PCI address...
Page 7 Section 6.2.2 - Referred user to the Fibre Channel Physical Interfaces speciﬁcation (FC-PI, Rev. 11) for Fibre Channel Interface Timings. Appendix B, Table 6.8 - Updated the list of Reference Speciﬁcations. Preface Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 9: Table Of Contents
Link Controllers 1.3.7 Transmitters 1.3.8 Receivers 1.3.9 Context Managers Initiator Operations Target Operations Diagnostics Chapter 2 Fibre Channel Overview Introduction FC Layers Frames LSIFC929 Dual Channel Fibre Channel I/O Processor Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 10 5.3.3 Memory Write and Invalidate Command 5.3.4 Read Commands Unsupported PCI Commands Programming Model PCI/Multifunction PCI Conﬁguration Registers 5.6.1 Multifunction PCI Host Interface Registers 5-24 Shared Memory 5-32 Contents Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 11 FC Layers Link Control Frame Data Frame Exchange to Character FCP Exchange Write Event Trellis Point-to-Point Topology Fabric Topology Arbitrated Loop Topology LSIFC929 Block Diagram LSIFC929 Message Flow Contents Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 12 Absolute Maximum Stress Ratings Capacitance Input Signals (FAULT1/, FAULT0/, ROMSIZE[1:0], ARMEN/, FSELZ[1:0], MODE[7:0], SWITCH, HOTSWAPEN/) Operating Conditions Schmitt Input Signals (REFCLK, TESTRESET/, ZCLK, TCK, TDI, TRST/, TMS_CHIP, TMS_ICE) Contents Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 13 6-24 6.16 Alphanumeric Pad Listing by Signal Name 6-25 6.17 Maximum Allowable Ambient Temperature vs. Airﬂow 6-27 LSIFC929 Multifunction PCI Registers LSIFC929 Host Interface Registers Reference Speciﬁcations Contents xiii Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 15: Chapter 1 Introduction
Storage Area Network (SAN) environment is fully supported with both Fibre Channel Protocol for SCSI (FCP) and LAN/IP. 1.1.1 Hardware Features Following is a list of hardware features supported by the LSIFC929. • Highly integrated full duplex Dual Channel Fibre Channel I/O Processor •...
Page 16: Fc Features
• JTAG debug interface • 329-pin BGA 1.1.2 FC Features Following is a list of Fibre Channel features supported by the LSIFC929. • Class 2 support and Class 3 support (with optional conﬁrmed delivery) • BB credit of 3, alternate login of 1 (each channel) •...
Page 17: Software Features
1.1.3 Software Features Following is a list of software features supported by the LSIFC929. • Fusion-MPT drivers • Supports optimum server I/O proﬁle with low CPU utilization • Supports optimum workstation I/O proﬁle with maximum I/O performance • Remote diagnostic capability •...
Page 18: General Description
CPU and PCI bandwidth required to support FC I/O operations. From the host CPU perspective, the LSIFC929 manages the FC Link at the exchange level for mass storage (FCP) protocols. The LSIFC929 supports multiple I/O requests per host interrupt in most applications.
Page 19: Multifunction Pci
The LSIFC929 supports two PCI functions and FC ports, which improves performance and provides a redundant path in high-availability systems that require failover capabilities. In case of a Link Failure, the LSIFC929 architecture allows the OS driver to support automatic failover, without the need for IOC intervention.
Page 20: Hardware Overview
The LSIFC929 provides the performance and ﬂexibility to meet tomorrow’s FC connectivity requirements. The LSIFC929 and the LSI Logic software drivers provide superior performance and lower host CPU overhead than other competitive solutions. Because of its high level of integration and streamlined architecture, the LSIFC929 provides the highest level of performance in a more cost effective FC solution.
Page 21: Pci Interface
PBSRAM 1.3.1 PCI Interface The LSIFC929 uses a 64-bit (33 MHz or 64 MHz) PCI interface or a 32-bit (33 MHz or 64 MHz) PCI interface. In addition, support is provided for Dual Address Cycle (DAC), PCI power management, Subsystem Vendor ID and Vendor Product Data (VPD).
Page 22: I/O Processor
1 Mbyte of Flash ROM. 1.3.3 I/O Processor The LSIFC929 uses a 32-bit ARM RISC processor to control all system interface and message transport functionality. This frees the host CPU for other processing activity and improves overall I/O performance. The RISC processor and associated ﬁrmware have the ability to manage an...
Page 23: Transmitters
Alternate Login BB-Credit of 1 on each channel. 1.3.9 Context Managers The LSIFC929 uses an ARM RISC processor in each channel to support I/O context swap to external memory and FCP management for both Initiator and Target applications. Context operations include support for transmit and resource queue management as well as scatter/gather list management.
Page 25: Chapter 2 Fibre Channel Overview
2.1, define the physical media and transmission rates, encoding scheme, framing protocol and flow control, common services, and the Upper Level Protocol (ULP) interfaces. LSIFC929 Dual Channel Fibre Channel I/O Processor Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 26: Fc Layers
Frames, Sequences, and Exchanges. The meaning of the data being transmitted or received is transparent to the FC-2 layer. However, the context between any given set of frames is maintained at Fibre Channel Overview Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 27: Frames
( ) = Number of Bytes A Data frame is any frame which contains data in the payload ﬁeld. An example of a Data frame is the LOGIN frame. Frames Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 28: Exchanges
FC Frame is a collection of FC words. A FC Sequence is made up of one or more frames, and a FC Exchange is made up of one or more sequences. Fibre Channel Overview Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 29: Exchange To Character
Using the FCP for the SCSI ULP, these phases can be mapped into the other lower FC layers. Figure 2.5 shows the components that make up the FCP exchange. Exchanges Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 30: Fcp Exchange
SCSI’s DATA_OUT phase. When the Target has received the last Frame of the Data Sequence(s), it will send a Response Sequence containing one Frame to the Initiator, thus concluding the FCP Exchange. Fibre Channel Overview Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 31: Fc Ports
Fabric between the N_Ports: • Point-to-Point topology • Fabric topology • Arbitrated Loop topology FC-PH protocols are topology independent. Attributes of a Fabric may restrict operation to certain communication models. FC Ports Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 32: Point-To-Point Topology
L_Ports attached. Each line in the figure between L_Ports represents a single fibre. The lower configuration shows an Arbitrated Loop composed of three NL_Ports and one FL_Port (a Public Loop). Fibre Channel Overview Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 33: Classes Of Service
Class 3 is also a connectionless class (the data being delivered is not guaranteed). The frames can be received out of order. Class 3 uses only the R_RDY Ordered Set for ﬂow control. Classes of Service Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 34 Class 1 frames. N_Ports advertising Intermix capability must be capable of receiving Class 2 and Class 3 frames from other N_Ports while maintaining the original Class 1 Link. 2-10 Fibre Channel Overview Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 35: Chapter 3 Lsifc929 Overview
Section 3.6, “Support Components” 3.1 Introduction The LSI Logic LSIFC929 is used to connect a host to a high speed FC Link. The FCP ANSI standard, FC Private Loop Direct Attach, and Fabric Loop Attach proﬁles are supported with the use of a sophisticated ﬁrmware implementation.
Page 36: Data Flows
3.1.1 Data Flows The LSIFC929 uses a 64-bit (33 MHz or 66 MHz) PCI interface to pass control and data information between the system and the protocol controller. This interface is managed by the PCI Interface block, as...
Page 37: Message Interface
The LSIFC929 uses two types of messages to communicate with the system. Request messages are created by the system to “request” an action by the LSIFC929. Reply messages are used by the LSIFC929 to send status information back to the system. Request message data structures are up to 128 bytes in length.
Page 38: Message Flow
The host must also provide one message frame per target LUN, and prime the Reply Free FIFOs for each function with the physical address of these message frames. Once allocation has been completed, requests will ﬂow from the host to the LSIFC929, as represented below and in Figure 3.2.
Page 39: Scsi Message Class
The SCSI I/O path translates a SCSI CDB into an FCP exchange. All FC device and target discovery operations are managed completely within the LSIFC929. FC target devices are assigned a logical (bus, target ID) identiﬁer, and are accessed by the system as if they were parallel SCSI devices.
Page 40: Lan Message Class
The typical network driver stack in the system consists of a Socket Driver with a Transport Driver Interface, supported by TCP or UDP and IP drivers, and a Hardware Abstraction layer interface to the LSIFC929. The TCP driver provides data buffer segmentation. The IP driver provides...
Page 41: Target Message Class
FC Sequence/Frame FC Framer 3.5 Target Message Class The Target interface allows the LSIFC929 to be used as the system interface for FC bridge controllers. The LSIFC929 provides an FCP exchange level message interface that routes commands to the system.
Page 42: Support Components
LSIFC929 ﬁrmware, such as initialization and error recovery code. The mainline code is stored within the internal LRAM for performance reasons. The LSIFC929 uses a 32 bit nonmultiplexed memory bus to access the SSRAM. This memory bus has the capability to address up to 4 Mbytes of SSRAM.
Page 43: Flash Rom
SSRAM through the diagnostic interface. Details of this implementation are available in the LSI Logic Fusion-MPT speciﬁcation. Flash ROM is optional for the LSIFC929, but it is required for ﬁrmware storage if INT 0x13 boot software is used. Flash ROM also simpliﬁes OS driver requirements and implementations.
Page 45: Chapter 4 Signal Descriptions
Chapter 4 Signal Descriptions This chapter contains signal descriptions for the LSIFC929. A slash (/) indicates an active low signal, I/O = bidirectional signal, I = input signal, O = output signal, T/S = 3-state, and S/T/S = sustained 3-state.
Page 46: Lsifc929 Functional Signal Grouping
JTAG and DEVSEL/ TMS_CHIP Core Debug PERR/ TMS_ICE IDDTN REQ64/ PROC_DRVLS ACK64/ ARMEN/ PAR64 TESTRESET/ PCICLK MODE[7:0] ENUM/ ROMSIZE[1:0] 64EN/ Conﬁguration FSELZ[1:0] SWITCH ZCLK HOTSWAPEN/ Miscellaneous GPIO[3:0] LED[4:0]/ Signal Descriptions Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 47: Pci Interface
Target, but will monitor this pin when initiating transfers (i.e., the LSIFC929 presents itself as a 32-bit slave device, but operates as a 64-bit bus master). Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 48 5 V Tol Initialization Device Select is used as a chip BiDir PCI select in place of the upper 24 address lines during conﬁguration read and write transactions. Signal Descriptions Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 49 STOP/ S/T/S 5 V Tol Stop indicates that the selected target is BiDir PCI requesting the master to stop the current transaction. Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 50 LOW, indicates that PCI Function[1] is requesting service from its Host device driver. If the chip is conﬁgured as a single-function device, only INTA/ is used. Signal Descriptions Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 51 See also the description of the GPIO[2] pin in Table 4.5, page 4-14, for additional information regarding other operational capabilities of this signal. Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 52: Fibre Channel Interface
Output Disable, Channel0. This output when 4 mA asserted disables an external GBIC or MIA transmitter for channel0. This output is also used to clear a module fault. Signal Descriptions Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 53 B10, A10, 3.3 V BiDir GBIC and pluggable SFF optical module 8 mA Identiﬁers (channel1). w/pullup FC reference clock (106.25 MHz ± 100 ppm). REFCLK 3.3 V Schmitt Input Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 54: Memory Interface
FLASHCS/ 3.3 V FLASH Chip Select. This active-LOW chip BiDir select allows connection of a single 8-bit 4 mA FLASH ROM device. 4-10 Signal Descriptions Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 55 3.3 V Snooze Control. Asserting this output HIGH BiDir will cause a synchronous SRAM to enter its 4 mA lowest power state (not all RAMs support this function). 4-11 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 56: Conﬁguration Signals
ZClk source. When FSELZ[1] is HIGH, the internal ZClk tree is sourced directly from the ZCLK input signal. FSELZ[1:0] Internal ZClk REFCLK/2 REFCLK * 2/3 External ZCLK External ZCLK 4-12 Signal Descriptions Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 57 Mode[7:0] = 00xxxx10 == Fast SEPROM Autoload Mode[7:0] = 00xxxx01 == Firmware PCI Conﬁg Mode (ARMEN/ must also be low) Mode[7:0] = 00xxxx00 == PCI Conﬁg use default values 4-13 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 58: Miscellaneous Signals
When FSELZ[1] is high, the internal ZClk tree is sourced directly from the ZCLK input signal. FSELZ[1:0] Internal ZClk REFCLK/2 REFCLK * 2/3 External ZCLK External ZCLK 4-14 Signal Descriptions Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 59: Jtag Test And I/O Processor Debug
JTAG Test Mode Select. Schmitt w/pullup TMS_ICE 3.3 V CtxMgr Debug Test Mode Select. Schmitt w/pullup IDDTN Input QIDD Test Enable. w/”large” pulldown PROC_DRVLS Process Monitor Test Output Driver. 4-15 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 60: Power And Ground Pins
Analog power for integrated transceiver core. 2.5 V TXBVSS0 Analog ground for integrated transceiver core. 0 V TXBVDD1 Analog power for integrated transceiver core. 2.5 V 4-16 Signal Descriptions Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 61 2.5 V TXVSS0 Analog ground for integrated transceiver core. 0 V TXVDD1 Analog power for integrated transceiver core. 2.5 V TXVSS1 Analog ground for integrated transceiver core. 0 V 4-17 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 63: Chapter 5 Registers
Chapter 5 Registers This chapter provides a description of the registers in the LSIFC929 Fibre Channel PCI Protocol Controller chip. The chapter contains the following sections: • Section 5.1, “PCI Addressing” • Section 5.2, “PCI Bus Commands Supported” • Section 5.3, “PCI Cache Mode”...
Page 64: Pci Bus Commands Supported
“000” (for PCI Function 0) or “001” (for PCI Function 1), or the LSIFC929 will not respond. According to the PCI speciﬁcation, AD[10:8] are used for multifunction devices. The host processor uses the PCI conﬁguration space to initialize the LSIFC929.
Page 65: Pci Cache Mode
Register in PCI conﬁguration space. Cache Read commands cannot be disabled. Slaves, however, can alias the Memory Read Line and Memory Read Multiple commands to the Memory Read command. PCI Cache Mode Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 66: Support For Pci Cache Line Size Register
5.3.3.1 Alignment The LSIFC929 uses the calculated line size value to monitor the current address for alignment to the cache line size. When it is not aligned, the chip attempts to align to the cache boundary by using a noncache command.
Page 67 4. The chip must be aligned to a cache line boundary. When these conditions have been met, the LSIFC929 issues a Write and Invalidate command instead of a Memory Write command during all PCI write cycles.
Page 68: Read Commands
5.3.3.5 PCI Target Disconnect During a Write and Invalidate transfer, if the target device issues a disconnect the LSIFC929 relinquishes the bus and immediately tries to ﬁnish the transfer on another bus ownership. The chip will not issue another Write and Invalidate command on the next ownership unless the address is aligned.
Page 69: Unsupported Pci Commands
PCI-compliant registers is optional. In the LSIFC929, registers that are not supported are not writable and return all zeroes when read. Only those registers and bits that are currently supported by the LSIFC929 are described in this chapter. For more detailed information on PCI registers, please see the PCI Local Bus Speciﬁcation.
Page 70: Multifunction Pci
Function[0] and Function[1] have identical looking conﬁguration space memory maps, and most of the data reported in these registers by the LSIFC929 is also the same. The only exceptions are the Device ID, Class Code, Subsystem ID, and Subsystem Vendor ID. Each of these values can be set separately for each function within the serial EEPROM, which is downloaded into these registers before any conﬁguration cycles are...
Page 71 Within the host registers located in I/O space and Mem0, some of the registers are also aliased and some are unique to the different functions. The multifunction feature of the LSIFC929 can be disabled by setting bit 0 in the Hardware Conﬁguration entry in the serial EEPROM. This clears the multifunction bit in the PCI conﬁguration space, and the...
Page 72 Status/Command Register provides coarse control over a device’s ability to generate and respond to PCI cycles. When a zero is written to this register, the LSIFC929 is logically disconnected from the PCI bus for all accesses except conﬁguration accesses. Detected Parity Error (Read/Write)
Page 73 The default value of this bit is zero. This bit and bit 6 must be set to report address parity errors. Reserved Reserved for future use. PCI/Multifunction PCI Conﬁguration Registers 5-11 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 74 EPER Enable Parity Error Response (Read/Write) This bit allows the LSIFC929 to detect parity errors on the PCI bus and report these errors to the system. Only data parity checking is enabled. The LSIFC929 always generates parity for the PCI bus.
Page 75 EPROM. RevID Revision ID (Read Only) [7:0] This register speciﬁes device and revision identiﬁers. In the LSIFC929, the upper nibble will be 0b0000. The lower nibble reﬂects the current revision level of the device. Register: 0x00C BIST/Header/Latency/Cache Line Size Read/Write...
Page 76 IOBAdd (Most Signiﬁcant) IOBAdd (Least Signiﬁcant) IOMemSp Note that this register is only 32 bits, because I/O must be mapped into the lower 4 Gbytes of address space. 5-14 Registers Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 77 64-bit space. IOMemSp I/O or Memory Space Indicator (Read Only) This bit is set to “0” to indicate Memory Space mapping. PCI/Multifunction PCI Conﬁguration Registers 5-15 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 78 [27:24] of the PCI Conﬁg0 register). The default value indicated is 64 Kbytes, unless ﬁrmware programs a differ- ent value prior to PCI conﬁguration, or if programmed with the serial EPROM. 5-16 Registers Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 79 Indicates upper 32 bits of the 64-bit memory address width, and the location of memory required by the device. This allows the LSIFC929 to be mapped above the 4 Gbytes boundary. PCI/Multifunction PCI Conﬁguration Registers 5-17 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 80 PCI device resides. SVID Subsystem Vendor ID [15:0] These bits are used to uniquely identify the vendor manufacturing the add-in board or subsystem where this PCI device resides. 5-18 Registers Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 81 EMS (Enable Memory Space) bit in the Command register. Note: If ROMSIZE[1:0] = 11, then there is no Expansion ROM. PCI/Multifunction PCI Conﬁguration Registers 5-19 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 82 Reserved for future use. CapPtr Capabilities Pointer (Read Only) [7:0] These bits indicate the location of the ﬁrst extended capability register in the PCI conﬁguration space. Register: 0x038 Reserved 5-20 Registers Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 83 The value in this register tells which input of the system interrupt controller(s) the device’s interrupt pin has been connected to. Values in this register are speciﬁed by system architecture. PCI/Multifunction PCI Conﬁguration Registers 5-21 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 84 PMCap Power Management Capabilities (Read Only) [31:16] These bits indicate the power management states supported by the LSIFC929, and to which version of the PCI Power Management Interface Speciﬁcation the LSIFC929 complies. For more information, refer to the PCI Speciﬁcation.
Page 85 Power Management Control/Status (Read/Write) [7:0] These bits indicate various control/status information speciﬁc to the LSIFC929. For more information, refer to the PCI Speciﬁcation Register: 0x048–0x07F Reserved PCI/Multifunction PCI Conﬁguration Registers 5-23 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 86: Host Interface Registers
Disconnect-with-data (TRDY/ and STOP/ both asserted) after the ﬁrst transfer of any burst attempt. The LSIFC929 also speciﬁes an I/O space requirement of 128 bytes of I/O mapped space which the System is required to assign during PCI conﬁguration. The 128 bytes of I/O space are mapped onto the ﬁrst 128 bytes of Memory 0 space;...
Page 87 The Request FIFOs are internally combined between the two functions due to the fact that both FIFOs are managed by the single IOP microprocessor internal to the LSIFC929. A small piece of hardware logic places a stamp onto Message Frame Address (MFA) bit 2 indicating from which function the request originated.
Page 88 Host Diagnostic Register (e.g., to verify that the Write Sequence data sequence was correct or to verify that writes to the Host Diagnostic Register have been disabled). 5-26 Registers Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 89 This bit, when set to ‘1’, indicates that physical reset (POR, PCI, or Test Reset/) has occurred within the LSIFC929 device. This bit may be written to zero by a Host driver to help coordinate error/reset recovery Host Interface Registers 5-27 Copyright ©...
Page 90 ‘0’, they are properly terminated on the PCI bus, but are not NOP’d by the chip. Register: 0x00C Test Base Address Register Read/Write TBAddr 5-28 Registers Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 91 Std reply option – whenever the ReplyPostFIFO is not empty. – Alt reply option – whenever the Host Index Register not equal to the ReplyPostWrPtr register. Host Interface Registers 5-29 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 92 [2:1] Reserved for future use. Doorbell Interrupt Mask (Read/Write) This bit when set to ‘1’ masks the System Doorbell Interrupt condition (prevents the assertion of PCI INTA/). 5-30 Registers Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 93 Reply Free MFAs from the Host on writes. RepMFA Reply MFA (Read/Write) [31:0] Reads: Reply Post MFA (0xFFFFFFFF = EMPTY). Writes: Reply Free MFA. Host Interface Registers 5-31 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 94: Shared Memory
Host Index Value (Read/Write) [13:0] 5.8 Shared Memory A region of Shared Memory (LSIFC929 local memory mapped to System Addresses) is provided to allow the Host to write Request Message Frames into. This is the default method (PUSH model) for Request Message Frame transport, where the Host itself copies the Request Message Frame into the LSIFC929 local memory.
Page 95: Speciﬁcations
− 0.3 V Input Voltage + 0.3 – ± 150 Latch-up current – – Electrostatic discharge – 1.5 k MIL-STD 883C, Method 3015.7 LSIFC929 Dual Channel Fibre Channel I/O Processor Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 96: Capacitance
MODE[7:0], SWITCH, HOTSWAPEN/) Symbol Parameter Unit Test Conditions Input high voltage 0.7 V + 0.3 – − 0.3 Input low voltage 0.2 V – µA Input leakage – Speciﬁcations Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 97: Schmitt Input Signals
+ 0.3 – − 0.3 Input low voltage 0.2 V – − 8 mA Output high voltage Output low voltage 8 mA − 10 µA 3-state leakage – Electrical Requirements Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 98: Pci Input Signals (Pciclk, Gnt/, Idsel, Rst/)
1. Signals without pull-up resistors meet a 3 mA output current load. Signals requiring pull-ups meet a 6 mA output current load. The latter include, FRAME/, TRDY/, IRDY/, STOP/, PERR/, and, when used, AD[63:32], C_BE[7:4], and ACK64/. Speciﬁcations Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 99: Pci Output Signals (Par64, Req/, Req64/, Devsel Serr/, Inta/, Intb/)
1. Signals without pull-up resistors meet a 3 mA output current load. Signals requiring pull-ups meet a 6 mA output current load. The latter include, DEVSEL/, SERR/, INTA/, INTB/, and, when used, PAR64, and REQ64/. Electrical Requirements Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 100: Ac Timing
Figure 6.8 represent signal activity when the LSIFC929 accesses the PCI bus. The timings for the PCI bus are listed page 6-17. The LSIFC929 conforms to Revision 2.1 of the PCI Local Bus Speciﬁcation. The timing speciﬁcations are provided here for ease of reference only.
Page 101 (Driven by Master) Note: STOP/ is only asserted LOW if the Master attempts a burst (i.e., FRAME/ is still asserted LOW) or if the LSIFC929 issues a retry. AC Timing Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 102 (Driven by LSIFC929) DEVSEL/ (Driven by LSIFC929) IDSEL (Driven by Master) Note: STOP/ is only asserted LOW if the Master attempts a burst (i.e., FRAME/ is still asserted LOW.) Speciﬁcations Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 103: Operating Register Read
(Driven by LSIFC929) Note 1 DEVSEL/ (Driven by LSIFC929) Note: STOP/ is only asserted LOW if the Master attempts a burst (i.e., FRAME/ is still asserted LOW). AC Timing Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 104 DEVSEL/ (Driven by LSIFC929) Note: STOP/ is only asserted LOW if the Master attempts a burst (i.e., FRAME/ is still asserted LOW) or if the LSIFC929 issues a retry. 6-10 Speciﬁcations Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 105 Back-to-Back Read (Driven by System) REQ/ (Driven by LSIFC929) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSIFC929) AD[31:0] Addr Addr (Driven by LSIFC929 - Address; Data Data Target - Data) C_BE/ Byte Enable Byte Enable (Driven by LSIFC929) Data Addr Data Addr (Driven by LSIFC929 - Address;...
Page 106 (Driven by System) REQ/ (Driven by LSIFC929) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSIFC929) AD[31:0] Addr Data Addr Data (Driven by LSIFC929 - Address; Target - Data) C_BE/ Byte Byte (Driven by LSIFC929) Enable Enable Addr Data Addr Data (Driven by LSIFC929 - Address;...
Page 107 (Driven by System) REQ/ (Driven by LSIFC929) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSIFC929) AD[31:0] Addr Address Data (Driven by LSIFC929 - Address; Data Data Target - Data) C_BE/ Byte Byte Enable Enable (Driven by LSIFC929) Data Data Data...
Page 108 REQ/ (Driven by LSIFC929) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSIFC929) AD[31:0] Address Data Address Data Data (Driven by LSIFC929 - Address; Target - Data) C_BE/ Byte Byte Enable Enable (Driven by LSIFC929) Address Data Data Address Data (Driven by LSIFC929 - Address;...
Page 109 Read With 64-Bit Initiator and 64-Bit Target (Driven by System) REQ64/ (Driven by LSIFC929) FRAME/ (Driven by LSIFC929) AD[31:0] Address Address (Driven by LSIFC929 - Address; Data Data Target - Data) AD[63:32] Data Data (Driven by Target) C_BE[3:0/] Byte Enable...
Page 110: Bit Dual-Address Cycle
(Driven by LSIFC929 - Address; Parity Parity Target - Data) IRDY/ (Driven by LSIFC929) TRDY/ (Driven by Target) STOP/ (Driven by Target) DEVSEL/ (Driven by Target) ACK64/ (Driven by Target) 6-16 Speciﬁcations Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 111: Pci Interface Timings
CLK to shared signal output valid Side signal input setup time – – Side signal input hold time – – CLK to side signal output valid AC Timing 6-17 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 112 Fibre Channel Physical Interface speciﬁcation (FC-PI, Rev. 11). All hardware validation testing performed by LSI Logic guarantees that the LSIFC929 meets or exceeds the speciﬁcations contained in that document.
Page 113: Ssram Read/Write/Read Timing Waveforms
1. The settings of FSELZ[1:0] determine the minimum and maximum MCLK cycle time. The values shown above are for FSELZ[1:0] = 01 (MCLK = 70.833 MHz). AC Timing 6-19 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 114: Flash Rom Read Timing Waveforms
FSELZ[1:0] = 01 (MCLK = 70.833 MHz). 2. Address setup time defaults to one (1) MCLK but may be programmed to zero (0) MCLKs using the serial EEPROM. 6-20 Speciﬁcations Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 115: Flash Rom Write Timing Waveforms
2. Address setup time defaults to one (1) MCLK but may be programmed to zero (0) MCLKs using the serial EEPROM. 3. Programmed using the serial EEPROM. AC Timing 6-21 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 116 6.3 Packaging The signal locations for the 329 Ball Grid Array (BGA) are illlustrated in Figure 6.16. Table 6.16 lists the LSIFC929 signals in alphanumeric order by BGA position. Table 6.17 lists the LSIFC929 signals in alphanumerically by signal name. Figure 6.17 is the mechanical drawing of the package for the LSIFC929.
Page 117 AD[61] AD[58] AD[54] VSSIO AD[49] AD[47] AD[04] AD[00] C_BE[6]/ C_BE[4]/ AD[62] AD[59] AD[56] AD[52] AD[50] AD[48] ENUM/ 64EN/ AD[01] C_BE[7]/ C_BE[5]/ AD[63] AD[60] AD[57] AD[55] AD[53] AD[51] Packaging 6-23 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 118: Alphanumeric Pad Listing By Bga Position
C_BE[3]/ MD[07] AC23 AD[51] VSSC MA[15] VSSIO MD[10] MA[00] MA[16] AD[20] MD[13] MA[01] LIPRESET/ AD[16] FLASHCS/ MA[03] FAULT0/ IRDY/ RAMCS/ RXVDD0 ODIS0 STOP/ BWE[1]/ RXVSS0 VSSC VSSIO 6-24 Speciﬁcations Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 119: Alphanumeric Pad Listing By Signal Name
MA[20] PCI5VREF VDDC AD[60] AC19 MA[21] PCI5VREF VDDC AD[61] AA18 MCLK PCI5VREF VDDIO AD[62] AB18 MD[00] PCI5VREF VDDIO AD[63] AC18 MD[01] PCI5VREF VDDIO ADSC/ MD[02] PCI5VREF VDDIO Packaging 6-25 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 120: Mechanical Drawing
Figure 6.15 329-Pad Plastic Ball Grid Array Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code BL. 6-26 Speciﬁcations...
Page 121: Package Thermal Considerations
The maximum recommended junction temperature for the LSIFC929 is 115 ˚C. To that end, LSI Logic recommends that the customer use an appropriate heat sink for the LSIFC929, and that adequate airﬂow exists throughout the system.
Page 123: Register Summary
Appendix A Register Summary Tables A.1 and A.2 list the register summary for the LSIFC929. Table A.1 LSIFC929 Multifunction PCI Registers Register Name Address Read/Write Page Device ID/Vendor ID 0x000 Read Only Status/Command 0x004 Read/Write 5-10 Class Code/Revision ID 0x008...
Page 124: A.2 Lsifc929 Host Interface Registers
Read Only 5-32 Host Interrupt Mask Register 0x034 Read/Write 5-33 Request FIFO 0x040 Write Only 5-34 Reply FIFO 0x044 Read/Write 5-34 Host Index Register 0x050 Read/Write 5-35 Register Summary Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 125: Reference Speciﬁcations
Fibre Channel Arbitrated Loop (FC-AL-2) FC Private Loop Direct Attach (FC-PLDA) Fibre Channel Protocol for SCSI (FCP) GBIC PCI Local Bus Speciﬁcation LSIFC929 Dual Channel Fibre Channel I/O Processor Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 127: Glossary Of Terms And Abbreviations
Conﬁguration Refers to the way a computer is set up; the combined hardware components (computer, monitor, keyboard, and peripheral devices) that LSIFC929 Dual Channel Fibre Channel I/O Processor Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 128 Lowest level of the FC Physical standard, covering the physical characteristics of the interface and media. FC-1 Middle level of the FC-PH standard, deﬁning the 8B/10B encoding/decoding and transmission protocol. Glossary of Terms and Abbreviations Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 129 The computer system in which a SCSI host adapter is installed. It uses the SCSI host adapter to transfer information to and from devices attached to the SCSI bus. Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 130 An operating system performs basic tasks such as moving data to and from devices, and managing information in memory. It also provides the user interface. Glossary of Terms and Abbreviations Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 131 RAM are lost when the computer is turned off. Responder A FC term referring to the answering device. RISC Core LSIFC929 chips contain a RISC (Reduced Instruction Set Computer) processor, programmed through microcode scripts. Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 132 Controls the low level POST (Power On Self Test), and basic operation of the CPU and computer system. Target ID. Topology The logical and/or physical arrangement of stations on a network. Glossary of Terms and Abbreviations Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 133 X3T9 A technical committee of the Accredited Standards Committee X3, titled X3T9 I/O Interfaces. It is tasked with developing standards for moving data in and out of central computers. Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 135 Flash ROM read timing 6-20 configuration registers. See PCI configuration registers Flash ROM write timing 6-21 context manager FLASHCS/ 4-10 controller link memory LSIFC929 Dual Channel Fibre Channel I/O Processor IX-1 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 136 Latency 5-13, 5-21 PERR/ latency pinout 6-22 LED[4:0]/ 4-14 point-to-point topology link control frames 2-3, ports link controller Power Management Configuration 5-22 LIPRESET/ Power Management Control 5-22 IX-2 Index Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 137 5-26 Start-of-Frame (SOF) Status 5-10, 5-22 STOP/ Subsystem ID 5-18 ZCLK 4-14 Support Components 4-11 Flash ROM Serial EEPROM SSRAM Memory SWITCH/ System Doorbell Register 5-25 system interface IX-3 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 139: Customer Feedback
Thank you for your help in improving the quality of our documents. LSIFC909 Fibre Channel I/O Processor August 2001 Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Page 140 LSI Logic Corporation Technical Publications M/S E-198 Fax: 408.433.4333 Please tell us how you rate this document: LSIFC929 Dual Channel Fibre Channel I/O Processor Technical Manual. Place a check mark in the appropriate blank for each category. Excellent Good Average...
Page 141 You can ﬁnd a current list of our U.S. distributors, international distributors, and sales ofﬁces and design resource centers on our web site at http://www.lsilogic.com/contacts/na_salesofﬁces.html...

LSI LSIFC929 Technical Manual

Chapter 1 Introduction

Chapter 2 Fibre Channel Overview

Chapter 3 LSIFC929 Overview

Chapter 4 Signal Descriptions

Chapter 5 Registers

Chapter 6 Speciﬁcations

Register Summary

Appendix A Register Summary

Reference Speciﬁcations

Appendix B Reference Specifications

Glossary of Terms and Abbreviations

Appendix C Glossary of Terms and Abbreviations

Customer Feedback

Quick Links

Related Manuals for LSI LSIFC929

Summary of Contents for LSI LSIFC929

Table of Contents