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(TC)
register are set to the correct state so that a phase match exists. In
addition to the phase match condition, the Assert Data Bus bit (bit 0 in
register 0xFC01) must be set and the I/O signals must be deasserted for
the SCSI core to send data.
For each transfer, the data is loaded into the
Output Data (ODR)
register
(0xFC00) and the Assert REQ/ bit (0xFC03, bit 3) is set. The
microcontroller must then wait for the REQ/ bit (0xFC04, bit 5) to become
active. Once REQ/ goes active, the Phase Match bit (0xFC05, bit 3) is
checked and the Assert ACK/ bit (0xFC01, bit 4) is set. The REQ/ bit is
sampled until it becomes false and the microcontroller resets the Assert
ACK/ bit to complete the transfer.
In addition to target send, programmed I/O transfers can also be used
for target receive, initiator send, and initiator receive operations.
Figure 2.5
illustrates target send and receive operations.
SCSI Core Operation
2-9
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