Table of Contents
Advertisement
4-10
SEL
Select
DBP
Data Bus Parity
Register: 0xFC04
Select Enable (SER)
Write Only
7
x
x
SE[7:0]
Selection ID bits
The Select Enable register is a write only register that is
used as a mask to monitor a single ID during a selection
attempt. The simultaneous occurrence of the
corresponding ID bit, BSY/ false and SEL/ true will cause
an interrupt. This interrupt can be disabled by resetting all
bits in this register and in the
register (0xFC0C). If the Enable Parity Checking bit
(register 0xFC02, bit 5) is active (1), parity will be
checked during selection.
Register: 0xFC05
Bus and Status (BSR)
Read Only
7
6
EOD
R
0
0
The Bus and Status register is a read only register that can be used to
monitor the remaining SCSI control signals not found in the
Bus Status (CSBS)
bits.
EOD
End of DMA Transfer
The End of DMA Transfer bit is set when a DMA transfer
completes. The REQ/ and ACK/ signals should be
monitored to ensure that the last byte has been
SCSI and DMA Registers
SE[7:0]
Defaults:
x
x
5
4
PERR
IRA
PMATCH
Defaults:
0
0
register (ATN/ and ACK/), as well as six other status
x
x
x
Select Enable High (SENHI)
3
2
1
BERR
ATN
x
0
SATN/
Current SCSI
1
0
0
x
[7:0]
0
ACK
SACK/
7
Advertisement
Table of Contents
