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2.3.4 SCSI - DMA Transfers
2.3.4.1 Halting a DMA Operation
In the SYM53C040, DMA handshaking with the SCSI core is handled
automatically by the DMA function. In order to initiate a DMA transfer to
the SCSI core using the DMA function in the SYM53C040, the following
sequence must be performed:
1. The
DMA Transfer Length (DTL)
Source/Destination Low (DSDL)
(DSDH)
address registers (0xFC11–0xFC13) must be written.
2. The
DMA Status (DS)
0 (TIP) position.
3. The firmware sets bit 0 in register 0x87 of the microcontroller core to
place the core in idle mode.
4. The DMA waits for the microcontroller to enter the idle mode before
taking over the internal bus for memory reads or writes.
5. Once the DMA receives a request from the SCSI core, the transfer
begins.
Figure 2.6
illustrates a target mode DMA transfer.
Any SCSI or DMA interrupt, if enabled in the
register, terminates the DMA cycle for the current bus phase. It is
recommended that the DMA Mode bit be reset after receiving an
interrupt. The DMA Mode bit must be set before writing any of the Start
DMA registers for subsequent bus phases.
SCSI Core Operation
register and the
and
DMA Source/Destination High
register (0xFC10) is written with a 1 in the bit
Interrupt Mask (IMR)
DMA
2-11
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