Interrupt Handling - LSI Symbios SYM53C040 Technical Manual

Table 2.6

Interrupt Handling

ISR Bit
Number Interrupt Source
7 SCSI core
6 Two-wire serial port 0
5 Two-wire serial port 1
4 DMA core
3 Timer 2
2 Timer 1
1 8067 Port 1 or MPIO3_1
0 8067 Port 0 or MPIO3_0
bits for determining the exact cause of the interrupt. This activity is
described in Table 2.6.
BSR (0xFC05)
CSBS (0xFC04)
CSD (0xFC00), CSDHI
(0xFC08)
Status (0xFD01)
Status (0xFD03)
DMAI (0xFC14)
T2C (0xFE09)
T1C (0xFE05)
MPI3
PCST1 (0xFC2A)
MPI3
PCST0 (0xFC22)
Interrupts
Location to read to
determine cause of
interrupt Description
Monitors SCSI bus control
signals not found in CSBS,
plus six other status bits.
Monitors SCSI bus control
lines plus data parity bit.
Reads the active SCSI bus.
Contains PIN bit plus other
status bits.
Contains PIN bit plus other
status bits.
Enables DMA interrupt.
Programs Timer 2, and
enables an interrupt upon
expiration of the timer.
Programs Timer 1, and
enables an interrupt upon
expiration of the timer.
Reads the values of
MPIO3_[1:0] pins, which also
serve as external interrupt
lines to the microcontroller
core.
Read Interrupt and Write
Interrupt status bits.
Reads the values of
MPIO3_[1:0] pins, which also
serve as external interrupt
lines to microcontroller core.
Read Interrupt and Write
Interrupt status bits.
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