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2.10.2.5 Loss of BSY/ Interrupt
2.10.3 SFF-8067 Interrupts
2.10.4 Two-Wire Serial Interrupts
and DBP/ will not be driven even though the Assert Data Bus bit is active.
This interrupt is only significant when the SYM53C040 is connected as
an initiator. It may be disabled by clearing the DMA Mode bit.
Note:
It is possible for this interrupt to occur when connected as
a target if another device is driving the phase lines to a
different state.
If the Monitor Busy bit (bit 2) in the
active, an interrupt will be generated if the BSY/ signal is asserted for at
least a bus settle delay (400 ns). This interrupt may be disabled by
resetting the Monitor Busy bit.
The SFF-8067 interface generates two types of interrupts: read interrupts
and write interrupts. The read interrupt notifies the SYM53C040 that the
Fibre Channel device is requesting data. The SYM53C040
microcontroller core should respond by clearing the interrupt and writing
one byte of data to the RDATA register, which is transferred to the
requesting drive. The write interrupt notifies the SYM53C040 that the
drive has written a byte of data to the interface. The SYM53C040
microcontroller core should respond by clearing the interrupt and reading
the WDATA register. The
(0xFC22/0xFC2A), bits [1:0] indicate whether a read or write interrupt
has occurred.
An interrupt from the Two-Wire Serial block is caused by one of the
following conditions:
•
A byte has been transferred (Status register 0xFD01/0xFD03, bit 3)
•
A Two-Wire Serial bus error (register 0xFD01/0xFD03, bit 4)
•
The chip is addressed as a slave (register 0xFD01/0xFD03, bit 2)
The External Interrupt Enable bit (0xFD01/0xFD03, bit 3) enables the
interrupt output to the microcontroller, while the Pending Interrupt bit (bit 7)
is clear. The PIN bit is active when the Two-Wire Serial interface has
completed an operation and requires processor intervention to continue.
Interrupts
Mode (MR)
Port Control/Status (PCST0/PCST1)
register (0xFC02) is
registers
2-31
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