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Table 3.9
Pin Assignments for SFF-8067 Mode (Cont.)
Pin/Ball
Signal Name
No.
DSK_WR/,
130/B9
SEL_6
PARALLEL_
129/C9
ESI/
PA0
127/D9
PA1
126/B10
PA2
125/C10
PA3
124/A11
PA4
119/D10
PA5
118/C12
PA6
117/D11
116/C13
tied to V
DD
tied to V
114/D12
DD
tied to V
113/D3
DD
Description
When PARALLEL_ESI/ is asserted,
this is an active low control signal
sourced by the drive to the
SYM53C040 to indicate the device
is ready to write data. When
PARALLEL_ESI/ is deasserted, this
signal is the SEL_6 signal, included
for compatibility with SFF-8045.
Used to select between the SEL_ID
and the bidirectional interface. Pull-
up resistors on the interface are 3.3
kΩζminimum. When this pin is
asserted, the drive begins the
discovery process and prepares to
read or write data. When this pin is
deasserted, the drive is presented
with SEL_ID. All SFF-8067
transactions are terminated,
regardless of the state of the
protocol.
This pin contains bit 0 of the
physical address of the enclosure.
This pin contains bit 1 of the
physical address of the enclosure.
This pin contains bit 2 of the
physical address of the enclosure.
This pin contains bit 3 of the
physical address of the enclosure.
This pin contains bit 4 of the
physical address of the enclosure.
This pin contains bit 5 of the
physical address of the enclosure.
This pin contains bit 6 of the
physical address of the enclosure.
SFF-8067 Mode
Port 1
Port 1
Port 0
Port 0
Port 0
Port 0
Port 0
Port 0
Port 0
–
N/A
–
N/A
–
N/A
Pad
8067 Port
Configuration
4 mA open drain
bidirectional
4 mA open drain
bidirectional
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
3-21
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