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4-12
ACK
Acknowledge
This bit reflects the condition of the SCSI bus control
signal ACK/. This signal is normally monitored by a target
device.
Register: 0xFC05
DMA Send (DSR)
Write Only
This register does not have individual bit definitions. Any write to this
register will initiate a DMA send, from the DMA core to the SCSI bus, for
either initiator or target role operations. The DMA Mode bit (register
0xFC02, bit 1) must be set prior to writing this register.
Register: 0xFC06
Start DMA Target Receive (SDTR)
Write Only
This register does not have individual bit definitions. Any write to this
register will initiate a DMA receive, from the SCSI bus to the DMA core,
for target operation only. The DMA Mode bit (register 0xFC02, bit 1) and
the Target Mode bit (register 0xFC02, bit 6) must both be set prior to
writing this register.
Register: 0xFC07
Reset Parity/Interrupt (RPI)
Read Only
This register does not have individual bit definitions. Any read to this
register resets the Parity Error bit (register 0xFC05, bit 5), the Interrupt
Request Active bit (register 0xFC05, bit 4) and the Busy Error bit
(register 0xFC05, bit 2).
Register: 0xFC07
Start DMA Initiator Receive (SDIR)
Write Only
This register does not have individual bit definitions. Any write to this
register will initiate a DMA receive from the SCSI bus, for initiator
operation only. The DMA Mode bit (register 0xFC02, bit 1) must be set
(1) and the Target Mode bit (register 0xFC02, bit 6) must be clear (0)
prior to writing this register.
SCSI and DMA Registers
0
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