Table of Contents
Advertisement
MB
Monitor Busy
The Monitor Busy bit, when set to a 1, causes an
interrupt to be generated for an unexpected loss of BSY/.
When the interrupt is generated due to loss of BSY/, the
lower 6 bits of the
(0xFC01) are reset and all signals are removed from the
SCSI bus.
DM
DMA Mode
The DMA Mode bit is used to enable a DMA transfer and
must be set to 1 prior to writing SCSI registers 0xFC05
through 0xFC07 to start DMA transfers. The Target Mode
bit (Mode register 0xFC02, bit 6) must be consistent with
writes to registers 0xFC06 and 0xFC07 (i.e., set to 1 for
a write to register 0xFC06 and reset for a write to register
0xFC07). The Assert Data Bus bit (register 0xFC01, bit
0) must be set to 1 for all DMA send operations. In the
DMA mode, REQ/ and ACK/ are automatically controlled.
The DMA Mode bit is not reset at the end of a DMA
transfer; DMA mode must be turned off by writing a 0 into
this bit location. However, care must be taken not to write
to any SCSI register during a DMA byte transfer.
Note:
The BSY/ signal must be active in order to set the DMA
Mode bit.
ARB
Arbitrate
The Arbitrate bit is set to 1 to start the arbitration process.
Prior to setting this bit, the
should contain the proper SCSI device ID value. Only one
data bit should be active for SCSI bus arbitration. The
SCSI core will wait for a bus free condition for entering
the arbitration phase. The results of the arbitration phase
may be determined by reading the status bits LA and AIP
(ICR register 0xFC01, bits 5 and 6 respectively). Write a
0 to this bit after completion of the arbitration phase.
Initiator Command (ICR)
Output Data (ODR)
2
register
1
0
register
4-7
Advertisement
Table of Contents
