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Table 3.9
Pin Assignments for SFF-8067 Mode (Cont.)
Pin/Ball
Signal Name
No.
ENCL_ACK/,
142/E7
SEL_4
DSK_RD/,
141/D7
SEL_5
DSK_WR/,
140/A7
SEL_6
PARALLEL_
139/B7
ESI/
D0, SEL_0
137/E8
Description
When PARALLEL_ESI/ is asserted,
this is an active low acknowledge
signal sourced by the SYM53C040
back to the Fibre Channel device.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_4
signal, included for compatibility with
SFF-8045.
When PARALLEL_ESI/ is asserted,
this is an active low control signal
sourced by the drive to the
SYM53C040 to indicate the device
is ready to read data. When
PARALLEL_ESI/ is deasserted, this
signal is the SEL_5 signal, included
for compatibility with SFF-8045.
When PARALLEL_ESI/ is asserted,
this is an active low control signal
sourced by the drive to the
SYM53C040 to indicate the device
is ready to write data. When
PARALLEL_ESI/ is deasserted, this
signal is the SEL_6 signal, included
for compatibility with SFF-8045.
Used to select between the SEL_ID
and the bidirectional interface. Pull-
up resistors on the interface are 3.3
kΩ minimum. When this pin is
asserted, the drive begins the
discovery process and prepares to
read or write data. When this pin is
deasserted, the drive is presented
with SEL_ID. All SFF-8067
transactions are terminated,
regardless of the state of the
protocol.
When PARALLEL_ESI/ is asserted,
this signal contains bit 0 of a data
nibble for read and write operations.
When PARALLEL_ESI/ is
deasserted, this signal is the SEL_0
signal, included for compatibility with
SFF-8045.
SFF-8067 Mode
8067 Port
Configuration
Port 0
4 mA open drain
bidirectional
Port 0
4 mA open drain
bidirectional
Port 0
4 mA open drain
bidirectional
Port 0
4 mA open drain
bidirectional
Port 1
4 mA open drain
bidirectional
Pad
3-19
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