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Register: 0xFE01
Watchdog Secondary Chain (WDSC)
Read Only
7
6
R
WDSC6
WDSC5
x
0
The values in this register are not affected by a soft reset.
R
Reserved
WDSC[6:0]
Watchdog Secondary Chain
These register bits provide the ability to read the 7-bit
value in the secondary watchdog timer divider chain. With
a 40 MHz external clock, this divider chain is clocked at
10 kHz (100 µ s per count).
Register: 0xFE02
Watchdog Final Chain (WDFC)
Read Only
7
R
x
x
The values in this register are not affected by a soft reset.
R
Reserved
WDFC[3:0]
Watchdog Final Chain
These register bits provide the ability to read the 4-bit
value in the final watchdog timer divider chain. With a
40 MHz external clock, this divider chain is clocked at
100 Hz (10 ms per count). The value in this register is
compared to the 4-bit value in bits 0 through 3 of the
Watchdog Timer Control (WDTC)
the time-out value of the watchdog timer.
5
4
3
WDSC4
WDSC3
Defaults:
0
0
0
4
3
WDFC3
Defaults:
x
x
0
2
1
WDSC2
WDSC1
WDSC0
0
0
2
1
WDFC2
WDFC1
WDFC0
0
0
register to determine
0
0
7
[6:0]
0
0
[7:4]
[3:0]
7-5
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