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T1CLR
Timer 1 Clear
A value of 1 in the T1CLR bit clears the timer. A value of
0 allows the timer to advance beyond the clear state.
T1PS
Timer 1 Prescaler
A value of 1 in the T1PS bit selects the additional divide
by 100 secondary divider chain, yielding a timer range of
0.5 ms to 128 ms with a resolution of 0.5 ms per step
(with a 40 MHz clock). A value of 0 bypasses the
secondary divider chain, yielding a timer range of 5 µ s to
1.280 ms with a resolution of 5 µ s per step.
R
Reserved
T1IEN
Timer 1 Interrupt Enable (read only)
A value of 1 in the T1IEN bit enables the timer to interrupt
the microcontroller core when the timer expires. This bit
is cleared upon chip reset.
Register: 0xFE06
Timer 1 Threshold (T1TH)
Read/Write
7
6
TITH7
TITH6
0
0
T1TH[7:0]
Timer 1 Threshold
These register bits select the time-out threshold for
timer 1. The 8-bit number programmed in this register
corresponds to a multiple of the selected timer resolution,
which is selected by the T1PS bit (0xFE05, bit 4). A value
of 0x00 in this register selects the maximum time-out
value of 256 times the selected timer resolution.
5
4
TITH5
TITH4
TITH3
Defaults:
0
0
3
2
1
TITH2
TITH1
0
0
0
5
4
[3:1]
0
0
TITH0
0
[7:0]
7-9
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