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Table 7.1
Miscellaneous Registers
31
7-2
Table
7.2, the register map, summarizes the Miscellaneous registers in
graphical form.
16 15
Watchdog Timer Control (WDTC)
Watchdog Secondary Chain (WDSC)
Watchdog Final Chain (WDFC)
Miscellaneous Control (MCR)
Interrupt Status (ISR)
Timer 1 Control (T1C)
Timer 1 Threshold (T1TH)
Timer 1 Secondary Chain (T1SC)
Timer 1 Final Chain (T1FC)
Timer 2 Control (T2C)
Timer 2 Threshold (T2T)
Timer 2 Secondary Chain (T2SC)
Timer 2 Final Chain (T2FC)
Interrupt Mask (IMR)
Interrupt Destination (IDR)
Reserved
Miscellaneous Registers
0
Address
0xFE00
0xFE01
0xFE02
0xFE03
0xFE04
0xFE05
0xFE06
0xFE07
0xFE08
0xFE09
0xFE0A
0xFE0B
0xFE0C
0xFE0D
0xFE0E
0xFEF0–0xFEF5
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