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busy
4-9
busy error
4-11
C_D
4-9
checksum error
6-9
chip revision
7-6
CKSUM
6-9
command/data
4-9
CTL0
6-11
CTL1
6-10
current SCSI data bus
current SCSI data high
D[3:0]
5-6
5-7
,
D[7:0]
6-4
data bits
6-4
data bus parity
4-10
data transfer length
4-15
DB[7:0]
4-3
5-3
,
DBP
4-10
DLADR[2:0]
8-6
DLCFG
8-4
DLSEL
8-6
DM
4-7
DMA interrupt
4-17
7-7
,
DMA mode
4-7
DMA source/destination high
DMA source/destination Low
DMA_INT
7-7
download configuration select
download ROM address
download serial ROM
DSDH[7:0]
4-16
DSDL[7:0]
4-16
DSK_RD/ value
5-6
5-7
,
DSK_WR/ value
5-5
,
DTL[7:0]
4-15
DWR/
5-5
5-7
,
EIEN
8-8
enable parity checking
enable parity interrupt
enable reset output
8-7
enable serial output
6-5
ENCL_ACK/ value
5-6
end of DMA transfer
ENI
6-5
6-7
,
EOD
4-10
EPC
4-6
EPI
4-6
ERO
8-7
ES[1:2]
6-5
6-7
,
ES0
6-5
6-6
,
EXS0_INT
7-8
EXS1_INT
7-8
external interrupt enable
IX-6
4-3
4-13
7-14
7-15
,
,
4-16
4-16
8-6
8-6
8-4
5-7
4-6
4-6
6-6
,
5-7
,
4-10
6-5
6-7
8-8
,
,
Index
fast blink rate
8-7
FBR[1:0]
8-7
FIBD[1:0]
8-4
first instruction branch destination
high impedance mode
7-6
I/O direction
4-14
I_O
4-9
ICF
6-3
IDR[7:0]
7-15
IEN
4-14
IMR[7:0]
7-13
input/output
4-9
INT
4-17
intermediate clock frequency
interrupt enable
4-14
interrupt request active
4-11
IOD
4-14
IRA
4-11
ITF0 control
6-11
ITF0 SCL input
6-11
ITF0 SCL output
6-11
ITF0 SDA input
6-11
ITF0 SDA output
6-11
ITF1 control
6-10
ITF1 SCL input
6-10
ITF1 SCL output
6-10
ITF1 SDA input
6-10
ITF1 SDA output
6-10
LA
4-4
LAB
6-9
last byte sent
4-8
last received bit
6-8
LBS
4-8
lost arbitration
4-4
6-9
,
LRB/AD0
6-8
LVD
8-8
LVD_PWRDWN
7-6
MB
4-7
message
4-9
MLI1_[3:0]
8-26
MLI1_[7:4]
8-27
MLI2_[3:0]
8-30
MLI2_[7:4]
8-31
MLL0_[3:0]
8-22
8-24
,
MLL0_[7:4] bits
8-23
8-25
,
MLL1_[3:0] bits
8-28
MLL1_[7:4] bits
8-29
MLL2_[3:0]
8-32
MLL2_[7:4]
8-33
MLLM0_[3:0]
8-23
MLLM0_[7:4]
8-24
MLLM1_[3:0]
8-27
MLLM1_[7:4]
8-28
8-4
6-3
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