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LSI LSI53C810A Technical Manual

Pci to scsi i/o processor
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TECHNICAL
MANUAL
LSI53C810A
PCI to SCSI I/O
Processor
Version 2.1
M a r c h 2 0 0 1
®
S14067

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Summary of Contents for LSI LSI53C810A

  • Page 1 TECHNICAL MANUAL LSI53C810A PCI to SCSI I/O Processor Version 2.1 M a r c h 2 0 0 1 ® S14067...
  • Page 2 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.
  • Page 3 Preface This book is the primary reference and technical manual for the LSI Logic LSI53C810A PCI to SCSI I/O Processor. It contains a complete functional description for the product and includes complete physical and electrical specifications. Audience This manual provides reference information on the LSI53C810A PCI to SCSI I/O processor.
  • Page 4 Chapter 6, Instruction Set of the I/O SCSI SCRIPTS instructions that are supported by the LSI53C810A. Chapter 7, Electrical characteristics and AC timings for the chip. Appendix A, Register Related Publications For background please contact: ANSI 11 West 42nd Street...
  • Page 5 Hexadecimal numbers are indicated by the prefix “0x” —for example, 0x32CF. Binary numbers are indicated by the prefix “0b” —for example, 0b0011.0010.1100.1111. Revision Record Revision Date Remarks 6/95 First version. 7/96 Revised technical manual. 3/01 All product names changed from SYM to LSI. Preface...
  • Page 6 Preface...

  • Page 7: Table Of Contents

    Contents Chapter 1 General Description TolerANT LSI53C810A Benefits Summary 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 1.2.6 1.2.7 Chapter 2 Functional Description SCSI Core 2.1.1 SCRIPTS Processor 2.2.1 Prefetching SCRIPTS Instructions 2.3.1 PCI Cache Mode 2.4.1 2.4.2 2.4.3 Parity Options 2.5.1 SCSI Bus Interface 2.6.1...
  • Page 8 Interrupt Handling 2.7.1 Chapter 3 PCI Functional Description PCI Addressing 3.1.1 3.1.2 PCI Cache Mode 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 Configuration Registers Chapter 4 Signal Descriptions PCI Bus Interface Signals 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 SCSI Bus Interface Signals 4.2.1 4.2.2 Chapter 5 Operating Registers...
  • Page 9 6.4.1 6.4.2 Read/Write Instructions 6.5.1 6.5.2 6.5.3 6.5.4 Transfer Control Instructions 6.6.1 6.6.2 Memory Move Instructions 6.7.1 6.7.2 6.7.3 6.7.4 Load and Store Instructions 6.8.1 6.8.2 Chapter 7 Electrical Characteristics DC Characteristics TolerANT Technology AC Characteristics PCI Interface Timing Diagrams 7.4.1 7.4.2 PCI Interface Timing...
  • Page 10 7.18 7.19 7.20 Contents LSI53C810A System Diagram LSI53C810A Chip Block Diagram DMA FIFO Sections LSI53C810A Host Interface Data Paths Active or Regulated Termination Determining the Synchronous Transfer Rate LSI53C810A Pin Diagram Functional Signal Grouping Register Address Map SCRIPTS Overview Block Move Instruction Register...
  • Page 11 7.21 7.22 7.23 7.24 Tables Contents Target Asynchronous Send Target Asynchronous Receive Initiator and Target Synchronous Transfers 100 LD PQFP (UD) Mechanical Drawing (Sheet 1 of 2) Bits Used for Parity Control and Observation SCSI Parity Control SCSI Parity Errors and Interrupts PCI Bus Commands and Encoding Types PCI Configuration Register Map Power and Ground Signals...
  • Page 12 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 Contents Bidirectional Signals—AD[31:0], C_BE/[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR/ Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/ TolerANT Technology Electrical Characteristics Clock Timing Reset Input Timing Interrupt Output PCI Timing Initiator Asynchronous Send (5 Mbytes/s) Initiator Asynchronous Receive (5 Mbytes/s) Target Asynchronous Send (5 Mbytes/s)

  • Page 13: Chapter 1 General Description

    SCSI to any PCI system. The LSI53C810A is a pin-for-pin replacement for the LSI53C810 PCI to SCSI I/O processor. It performs fast SCSI transfers in Single-Ended (SE) mode, and improves performance by optimizing PCI bus utilization.

  • Page 14: Tolerant ® Technology

    SCSI operations. The TolerANT input signal filtering is a built in feature of all LSI Logic fast SCSI devices. On the LSI53C8XX family products, the user may select a filtering period of 30 or 60 ns, with bit 1 in the Test Two (STEST2) The benefits of TolerANT technology include increased immunity to noise...

  • Page 15: Lsi53C810A Benefits Summary

    1.2 LSI53C810A Benefits Summary This section provides an overview of the LSI53C810A features and benefits. It contains these topics: SCSI Performance PCI Performance Integration Ease of Use Flexibility Reliability Testability 1.2.1 SCSI Performance To improve SCSI performance, the LSI53C810A: Complies with PCI 2.1 specification...

  • Page 16: Pci Performance

    Performs zero wait-state bus master data bursts faster than 110 Mbytes/s (@ 33 MHz) Supports PCI 1.2.3 Integration Features of the LSI53C810A which ease integration include: 3.3 V/5 V PCI interface Full 32-bit PCI DMA bus master DMA controller using Memory-to-Memory Move instructions...

  • Page 17: Flexibility

    Selectable IRQ pin disable bit Ability to route system clock to SCSI clock 1.2.6 Reliability Enhanced reliability features of the LSI53C810A include: 2 kV ESD protection on SCSI signals Typical 300 mV SCSI bus hysteresis Average operating supply current of 50 mA Protection against bus reflections due to impedance mismatches...

  • Page 18: Testability

    SCSI bus signal continuity checking Support for single step mode operation Test mode (AND tree) to check pin continuity to the board A system diagram showing the connections of the LSI53C810A in a PCI system is pictured in pictured in...

  • Page 19: Lsi53C810A System Diagram

    Figure 1.1 LSI53C810A System Diagram SCSI Connection SCSI Term Connection SCSI Bus PCI Bus LSI53C810A Peripheral 40 MHz Oscillator or Optional Internal Bulkhead Connection to PCI Bus Clock CPU Baseboard CPU Box LSI53C810A Benefits Summary...

  • Page 20: Lsi53C810A Chip Block Diagram

    Figure 1.2 LSI53C810A Chip Block Diagram PCI Master and Slave Control Block Data Configuration Operating SCSI FIFO Registers Registers SCRIPTS 80 Bytes SCSI FIFO and SCSI Control Block TolerANT Technology Drivers and Receivers SE SCSI Bus General Description...

  • Page 21: Chapter 2 Functional Description

    Section 2.6, “SCSI Bus Interface” Section 2.7, “Interrupt Handling” The LSI53C810A contains three functional blocks: the SCSI Core, the DMA Core, and the SCRIPTS Processor. The LSI53C810A is fully supported by the SDMS, a complete software package that supports the LSI Logic product line of SCSI processors and controllers.

  • Page 22: Dma Core

    SCRIPTS processor, which supports uninterrupted scatter/gather memory operations. The LSI53C810A supports 32-bit memory and automatically supports misaligned DMA transfers. An 80-byte FIFO allows 2, 4, 8, or 16 Dword bursts across the PCI bus interface to run efficiently without throttling the bus during PCI bus latency.

  • Page 23: Sdms Software: The Total Scsi Solution

    Set of the I/O Processor.” 2.2.1 SDMS Software: The Total SCSI Solution For users who do not need to develop custom drivers, LSI Logic provides a total SCSI solution in PC environments with SDMS software. SDMS software provides BIOS and driver support for hard disk, tape, and removable media peripherals for the major PC-based operating systems.

  • Page 24: Opcode Fetch Burst Capability

    Chapter 6, “Instruction Set of the I/O DMA SCRIPTS Pointer (DSP) (DMA Control (DCNTL) register (0x38) causes the LSI53C810A to burst in the first two This feature can only be used if SCRIPTS prefetching is disabled. register, the PCI commands Read Line, Read Multiple, and register.

  • Page 25: Load And Store Instructions

    Chapter 6, “Instruction Set of the I/O Processor.” 2.4.2 3.3 V/5 V PCI Interface The LSI53C810A can attach directly to a 3.3 V or a 5 V PCI interface, due to separate V to be used on the universal board recommended by the PCI Special Interest Group.
  • Page 26 Data Latch (SIDL) Enables parity checking during master data phases. Set when the LSI53C810A, as a PCI master, detects a target device signaling a parity error during a data phase. By clearing this bit, a Master Data Parity Error does not...

  • Page 27: Scsi Parity Errors And Interrupts

    Table 2.2 SCSI Parity Control AESP 1. Key: EPC = Enable Parity Checking (bit 3, ASEP = Assert SCSI Even Parity (bit 2, Table 2.3 SCSI Parity Errors and Interrupts Key: DHP = Disable Halt on SATN/ or Parity Error (bit 5, PAR = Parity Error (bit 0, SCSI Interrupt Enable Zero This table only applies when the Enable Parity Checking bit is set.

  • Page 28: Dma Fifo

    Figure 2.1 Bytes Deep 2.5.1.1 Data Paths The data path through the LSI53C810A is dependent on whether data is being moved into or out of the chip, and whether SCSI data is being transferred asynchronously or synchronously. Figure 2.2 different modes.
  • Page 29 Asynchronous SCSI Send – Step 1. Look at the DMA FIFO (DFIFO) registers and calculate if there are bytes left in the DMA FIFO. To make this calculation, subtract the seven least significant bits of the DMA Byte Counter (DBC) DMA FIFO (DFIFO) a byte count between zero and 80.

  • Page 30: Lsi53C810A Host Interface Data Paths

    SCSI Status One (SSTAT1) [7:4], the binary representation of the number of valid bytes in the SCSI FIFO, to determine if any bytes are left in the SCSI FIFO. LSI53C810A Host Interface Data Paths Interface DMA FIFO (4-bytes x 20)

  • Page 31: Scsi Bus Interface

    2.6 SCSI Bus Interface The LSI53C810A supports SE operation only. All SCSI signals are active LOW. The LSI53C810A contains the SE output drivers and can be connected directly to the SCSI bus. Each output is isolated from the power supply to ensure that a powered-down LSI53C810A has no effect on an active SCSI bus (CMOS “voltage feed-through”...

  • Page 32: Active Or Regulated Termination

    Set Target instruction. The Selection and Reselection Enable bits (SCSI Chip ID (SCID) so that the LSI53C810A may respond as an initiator or as a target. If only selection is enabled, the LSI53C810A cannot be reselected as an initiator.

  • Page 33: Synchronous Operation

    CPU before SCRIPTS execution begins, from within SCRIPTS using a Table Indirect I/O instruction, or with a Read-Modify-Write instruction. The LSI53C810A can receive data from the SCSI bus at a synchronous transfer period as short as 80 ns or 160 ns (with a 50 MHz clock), regardless of the transfer period used to send data.
  • Page 34 2.6.3.3 SCNTL3 Register, Bits [2:0] (CCF[2:0]) The CCF[2:0] bits select the frequency of the SCLK for asynchronous SCSI operations. To meet the SCSI timings as defined by the ANSI specification, these bits need to be set properly. 2.6.3.4 SXFER Register, Bits [7:5] (TP[2:0]) The TP[2:0] divider (XFERP) bits determine the SCSI synchronous send rate in either initiator or target mode.

  • Page 35: Interrupt Handling

    However, certain interrupt situations must be handled by the external microprocessor. This section explains all aspects of interrupts as they apply to the LSI53C810A. 2.7.1 Polling and Hardware Interrupts The external microprocessor is informed of an interrupt condition by polling or hardware interrupts.
  • Page 36 Reading these registers determines which condition or conditions caused the SCSI-type interrupt, and clears that SCSI interrupt condition. If the LSI53C810A is receiving data from the SCSI bus and a fatal interrupt condition occurs, the LSI53C810A attempts to send the contents of the DMA FIFO to memory before generating the interrupt.
  • Page 37 If the LSI53C810A is sending data to the SCSI bus and a fatal SCSI interrupt condition occurs, data could be left in the DMA FIFO. Because of this the DMA FIFO Empty (DFE) bit in checked. If this bit is cleared, set the CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits before continuing.
  • Page 38 CPU. This prevents an interrupt when arbitration is complete (CMP set), when the LSI53C810A is selected or reselected (SEL or RSL set), when the initiator asserts ATN (target mode: SATN/ active), or when the General Purpose or Handshake-to-Handshake timers expire.
  • Page 39 IRQ/. 2.7.1.4 Stacked Interrupts The LSI53C810A will stack interrupts if they occur one after the other. If the SIP or DIP bits in the ISTAT register are set (first level), then there is already at least one pending interrupt, and any future interrupts are...
  • Page 40 These ‘locked out’ SCSI interrupts are posted as soon as the DMA FIFO is empty. 2.7.1.5 Halting in an Orderly Fashion When an interrupt occurs, the LSI53C810A attempts to halt in an orderly fashion. If the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a Bus Fault.
  • Page 41 All other instructions may halt before completion. 2.7.1.6 Sample Interrupt Service Routine The following is a sample of an interrupt service routine for the LSI53C810A. It can be repeated during polling or should be called when the IRQ/ pin is asserted if hardware interrupts. 1. Read 2.
  • Page 42 consecutive reads to ensure that the interrupts clear properly. Both the SCSI and DMA interrupt conditions should be handled before leaving the ISR. It is recommended that the DMA interrupt is serviced before the SCSI interrupt, because a serious DMA interrupt condition could influence how the SCSI interrupt is acted upon.

  • Page 43: Chapter 3 Pci Functional Description

    8-bit register. The host processor uses this configuration space to initialize the LSI53C810A. The lower 128 bytes of the LSI53C810A configuration space hold system parameters while the upper 128 bytes map into the LSI53C810A operating registers. For all PCI cycles except configuration cycles, the LSI53C810A registers are located on the 256-byte block boundary defined by the base address assigned through the configured register.

  • Page 44: Pci Bus Commands And Functions Supported

    128-byte portions of the 256-byte space selected. At initialization time, each PCI device is assigned a base address for memory and I/O accesses. In the case of the LSI53C810A, the upper 24 bits of the address are selected. On every access, the LSI53C810A compares its assigned base addresses with the value on the Address/Data bus during the PCI address phase.

  • Page 45: Pci Cache Mode

    All 32 address bits are decoded. 3.2 PCI Cache Mode The LSI53C810A supports the PCI specification for an 8-bit Size register located in PCI configuration space. The register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries.

  • Page 46: Selection Of Cache Line Size

    3.2.3.1 MMOV Misalignment The LSI53C810A does not operate in a cache alignment mode when a MMOV instruction is issued and the read and write addresses are different distances from the nearest cache line boundary. For example, if...
  • Page 47 The chip has enough bytes in the DMA FIFO to complete at least one full cache line burst. The chip is aligned to a cache line boundary. When these conditions are met, the LSI53C810A issues a Write and Invalidate command instead of a Memory Write command during all PCI write cycles.
  • Page 48 PCI specification. PCI Target Disconnect – During a Write and Invalidate transfer, if the target device issues a disconnect the LSI53C810A relinquishes the bus and immediately tries to finish the transfer on another bus ownership. The chip does not issue another Write and Invalidate command on the next ownership.

  • Page 49: Memory Read Multiple Command

    This command is identical to the Memory Read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. The LSI53C810A supports PCI Read Multiple functionality and issues Read Multiple commands on the PCI bus when the Read Multiple Mode is enabled.

  • Page 50: Unsupported Pci Commands

    Read Multiple commands are issued if the Read Multiple conditions are met. 3.2.5 Unsupported PCI Commands The LSI53C810A does not respond to reserved commands, special cycle, dual address cycle, or interrupt acknowledge commands as a slave. It never generates these commands as a master.

  • Page 51: Configuration Registers

    No other cycles, including SCRIPTS operations, can access these registers. The lower 128 bytes hold configuration data while the upper 128 bytes hold the LSI53C810A operating registers, which are described in Chapter 5, “Operating Registers.” accessed by SCRIPTS or the host processor.

  • Page 52: Pci Configuration Register Map

    PCI-compliant registers is optional. In the LSI53C810A, registers that are not supported are not writable and return all zeros when read. Only those registers and bits that are currently supported by the LSI53C810A are described in this chapter. Table 3.2 the LSI53C810A.
  • Page 53 PCI cycles. When a zero is written to this register, the LSI53C810A is logically disconnected from the PCI bus for all accesses except configuration accesses. In the LSI53C810A, bits 3, 5, 7, and 9 are not implemented. Bits 10 through 15 are reserved. Configuration Registers...
  • Page 54 PCI bus. A value of zero disables the device from generating PCI bus master accesses. A value of one allows the LSI53C810A to behave as a bus master. The LSI53C810A must be a bus master in order to fetch SCRIPTS instructions and transfer data.
  • Page 55 The Status register is used to record status information for PCI bus-related events. In the LSI53C810A, bits 0 through 4 are reserved and bits 5, 6, 7, and 11 are not implemented. Reads to this register behave normally. Writes are slightly different in that bits can be cleared, but not set.
  • Page 56 These bits are read only and should indicate the slowest time that a device asserts DEVSEL/ for any bus command except Configuration Read and Configuration Write. The LSI53C810A supports 0b01. Data Parity Reported This bit is set when the following three conditions are...
  • Page 57 Configuration Registers Revision ID This register specifies device and revision identifiers. In the LSI53C810A, the upper nibble is 0001b. The lower nibble represents the current revision level of the device. It should have the same value as the Chip Revision Level...
  • Page 58 Cache Line Size Enable (CLSE) bit, bit 7 in the Control (DCNTL) register. Setting this bit causes the LSI53C810A to align to cache line boundaries before allowing any bursting, except during MMOVs in which the read and write addresses are Burst Size boundary misaligned.
  • Page 59 Register: 0x0E Header Type Read Only Register: 0x10 Base Address Zero (I/O) Read/Write BARZ Register: 0x14 Base Address One (Memory) Read/Write BARO Configuration Registers Header Type This register identifies the layout of bytes 0x10 through 0x3F in configuration space and also whether or not the device contains multiple functions.
  • Page 60 Register: 0x3C Interrupt Line Read/Write Register: 0x3D Interrupt Pin Read Only 3-18 PCI Functional Description Interrupt Line This register is used to communicate interrupt line routing information. POST software writes the routing information into this register as it initiates and configures the system. The value in this register tells which input of the system interrupt controller(s) the device’s interrupt pin is connected to.
  • Page 61 The value specified in this register is in units of 0.25 microseconds. Values of zero indicate that the device has no major requirements for the settings of Latency Timers. The LSI53C810A sets the Min_Gnt register to 0x11. Register: 0x3F...
  • Page 62 3-20 PCI Functional Description...

  • Page 63: Chapter 4 Signal Descriptions

    Chapter 4 Signal Descriptions This chapter presents the LSI53C810A pin configuration and signal definitions using tables and illustrations. Figure 4.2 is a functional signal grouping. The pin definitions are presented in Table 4.1 through compatible with the LSI53C810. This chapter is divided into the following sections: Section 4.1, “PCI Bus Interface Signals”...

  • Page 64: Lsi53C810A Pin Diagram

    A slash (/) at the end of the signal name indicates that the active state occurs when the signal is at a LOW voltage. When the slash is absent, the signal is active at a HIGH voltage. Signal Descriptions LSI53C810A Pin Diagram LSI53C810A 100-pin Quad Flat Pack...

  • Page 65: Power And Ground Signals

    Signals are assigned a type. There are four signal types: S/T/S Table 4.1 Table 4.1 Power and Ground Signals Name Pin No. 5, 9, 13, 18, 22, 26, 32, 37, 43, SS-I 87, 93, 99 3, 16, 28, 40, 90 DD-I 58, 63, 68, 73 SS-S...

  • Page 66: Address And Data Signals

    Figure 4.2 Functional Signal Grouping System AD[31:0] Address C_BE/[3:0] Data FRAME/ TRDY/ Interface IRDY/ Control STOP/ DEVSEL/ IDSEL REQ/ Arbitration GNT/ PERR/ Error Reporting SERR/ Signal Descriptions SCLK SD[7:0] SCTRL/ TESTIN/ GPIO0_FETCH/ GPIO1_MASTER/ MAC/_TESTOUT IRQ/ SCSI Additional Interface...

  • Page 67: Address And Data Signals

    4.1 PCI Bus Interface Signals The PCI signal definitions are organized into the following functional groups: Signals, Reporting 4.1.1 System Signals Table 4.2 Table 4.2 System Signals Name Pin No. Type Description Clock provides timing for all transactions on the PCI bus and is an input to every PCI device.

  • Page 68: Address And Data Signals

    4.1.2 Address and Data Signals Table 4.3 Table 4.3 Address and Data Signals Name Pin No. AD[31:0] 85, 86, 88, 89, 91, 92, 94, 95, 98, 100, 1, 2, 4, 6, 7, 8, 23, 24, 25, 27, 29, 30, 31, 33, 35, 36, 38, 39, 41, 42, 44, 45 C_BE/[3:0] 96, 10, 21, 34...

  • Page 69: Interface Control Signals

    4.1.3 Interface Control Signals Table 4.4 Table 4.4 Interface Control Signals Name Pin No. Type FRAME/ S/T/S TRDY/ S/T/S IRDY/ S/T/S STOP/ S/T/S DEVSEL/ 15 S/T/S IDSEL PCI Bus Interface Signals describes the Interface Control Signals group. Description Cycle Frame is driven by the current master to indicate the beginning and duration of an access.

  • Page 70: Arbitration Signals

    4.1.4 Arbitration Signals Table 4.5 Table 4.5 Arbitration Signals Name Pin No. Type Strength REQ/ 200, A4 16 mA PCI GNT/ 199, B5 4.1.5 Error Reporting Signals Table 4.6 Table 4.6 Error Reporting Signals Name Pin No. Type PERR/ 19 S/T/S SERR/ 78 Signal Descriptions...

  • Page 71: Additional Interface Signals

    4.2 SCSI Bus Interface Signals The SCSI signal definitions are organized into the following functional groups: 4.2.1 SCSI Bus Interface Signals Table 4.7 Table 4.7 SCSI Bus Interface Signals Name Pin No. SCLK SD[7:0], 67, 69, 70, 71, 72, 74, 75, 76, 66 SCTRL/ 57, 55, 60, 56, 62, 64, 65, 61, 59...

  • Page 72: Additional Interface Signals

    Signal Descriptions describes the Additional Interface Signals group. Test In. When this pin is driven LOW, the LSI53C810A connects all inputs and outputs to an “AND tree.” The SCSI control signals and data lines are not connected to the “AND tree.” The output of the “AND tree”...
  • Page 73 Memory Access Control. This pin can be programmed to indicate local or system memory accesses (non-PCI applications). It is also used to test the connectivity of the LSI53C810A signals using an “AND tree” scheme. The MAC/_TESTOUT pin is only driven as the Test Out function when the TESTIN/ pin is driven LOW.
  • Page 74 4-12 Signal Descriptions...

  • Page 75: Chapter 5 Operating Registers

    Chapter 5 Operating Registers This chapter describes all LSI53C810A operating registers. register map, lists registers by operating and configuration addresses. The terms “set” and “assert” are used to refer to bits that are programmed to a binary one. Similarly, the terms “deassert,” “clear,” and “reset”...

  • Page 76: Register Address Map

    Figure 5.1 Register Address Map SCNTL3 SCNTL2 GPREG SDID SBCL SSID SSTAT2 SSTAT1 Reserved CTEST3 CTEST2 CTEST6 CTEST5 DCMD DCNTL SIST1 SIST0 GPCNTL MACNTL Reserved RESPID STEST3 STEST2 Reserved Reserved Reserved Register: 0x00 (0x80) SCSI Control Zero (SCNTL0) Read/Write ARB[1:0] Operating Registers 16 15 SCNTL1...
  • Page 77 Arbitration Mode Bits 1 and 0 ARB1 ARB0 Simple Arbitration The LSI53C810A waits for a bus free condition to occur. It asserts SBSY/ and its SCSI ID (contained in the SCSI Chip ID (SCID) the SSEL/ signal is asserted by another SCSI...
  • Page 78 LSI53C810A is not connected to the SCSI bus. Select with SATN/ on a Start Sequence When this bit is set and the LSI53C810A is in the initiator mode, the SATN/ signal is asserted during selection of a SCSI target device. This is to inform the target that the LSI53C810A has a message to send.
  • Page 79 SCSI Interrupt Status Zero (SIST0) set and an interrupt may be generated. If the LSI53C810A is operating in the initiator mode and a parity error is detected, assertion of SATN/ is optional, but the transfer continues until the target changes phase.
  • Page 80 Setting this bit only affects SCSI send operations. Assert SCSI Data Bus When this bit is set, the LSI53C810A drives the contents of the SCSI Output Data Latch (SODL) SCSI data bus. When the LSI53C810A is an initiator, the...
  • Page 81 When this bit is set, the LSI53C810A does not halt the SCSI transfer when SATN/ or a parity error is received. Connected This bit is automatically set any time the LSI53C810A is connected to the SCSI bus as an initiator or as a target.
  • Page 82 Free phase immediately following the arbitration phase, it is possible to perform a low level selection instead. The abort completes because the LSI53C810A loses arbitration. This is detected by clearing the Immediate Arbitration bit. Do not use the Lost Arbitration bit (SCSI Status Zero (SSTAT0) condition.
  • Page 83 Register: 0x02 (0x82) SCSI Control Two (SCNTL2) Read/Write SCSI Disconnect Unexpected This bit is valid in the initiator mode only. When this bit is set, the SCSI core is not expecting the SCSI bus to enter the Bus Free phase. If it does, an unexpected disconnect error is generated (see the Unexpected Disconnect bit in SCSI Interrupt Status Zero (SIST0) During normal SCRIPTS mode operation, this bit is set...

  • Page 84: Synchronous Clock Conversion Factor

    Note: CCF[2:0] 5-10 Operating Registers determines the transfer rate. For example, if SCLK is 40 MHz and the SCF value is set to divide by one, then the maximum synchronous receive rate is 10 Mbytes/s ((40/1) /4 = 10). For synchronous send, the output of this divider gets divided by the transfer period (XFERP) bits in the Transfer (SXFER) register, and that value determines the...

  • Page 85: Asynchronous Clock Conversion Factor

    LSI53C810A does not automatically reconfigure itself to initiator mode as a result of being reselected. Enable Response to Selection When this bit is set, the LSI53C810A is able to respond to bus-initiated selection at the chip ID in the ID (RESPID) not automatically reconfigure itself to target mode as a...
  • Page 86 Operating Registers Reserved Encoded LSI53C810A Chip SCSI ID These bits are used to store the LSI53C810A encoded SCSI ID. This is the ID which the chip asserts when arbitrating for the SCSI bus. The IDs that the LSI53C810A responds to when being selected or reselected are configured in the...

  • Page 87: Examples Of Synchronous Transfer Periods And Rates For Scsi-1

    Use the following formula to calculate the synchronous send and receive rates. examples of possible bit combinations. Synchronous Send Rate = (SCLK/SCF)/XFERP Synchronous Receive Rate = (SCLK/SCF) /4 Where: SCLK SCSI clock Synchronous Clock Conversion Factor, SCNTL3 register, bits [6:4] XFERP Transfer period, SXFER register, bits [7:5] Table 5.3...

  • Page 88: Examples Of Synchronous Transfer Periods And Rates For Fast Scsi

    6.25 4.17 Reserved Max SCSI Synchronous Offset These bits describe the maximum SCSI synchronous offset used by the LSI53C810A when transferring synchronous SCSI data in either the initiator or target mode. Table 5.5 describes the possible combinations and their relationship to the synchronous data offset used by Synch.

  • Page 89: Scsi Synchronous Offset Values

    LSI53C810A. These bits determine the LSI53C810A’s method of transfer for Data-In and Data-Out phases only; all other information transfers occur asynchronously. Table 5.5 Register: 0x06 (0x86) SCSI Destination ID (SDID) Read/Write Reserved ENC[2:0] Encoded destination SCSI ID Writing these bits sets the SCSI ID of the intended initiator or target during SCSI reselection or selection phases, respectively.
  • Page 90 When configured as inputs, an internal pull-up is enabled. LSI Logic SDMS software uses the GPIO 0 pin to toggle SCSI device LEDs, turning on the LED whenever the LSI53C810A is connected to the SCSI bus. SDMS software drives this pin low to turn on the LED, or drives it high to turn off the LED.
  • Page 91 SCSI First Byte Received (SFBR) Read/Write This register contains the first byte received in any asynchronous information transfer phase. For example, when the a LSI53C810A is operating in initiator mode, this register contains the first byte received in Message-In, Status phase, Reserved-In and Data-In.
  • Page 92 SCSI SCRIPTS. transferring data using programmed I/O. Some bits are set (1) or cleared (0) when executing SCSI SCRIPTS. Do not write to the register once the LSI53C810A starts executing normal SCSI SCRIPTS. 5-18 Operating Registers Assert SCSI REQ/ Signal...
  • Page 93 ENID[2:0] Encoded Destination SCSI ID Reading the SSID register immediately after the LSI53C810A has been selected or reselected returns the binary-encoded SCSI ID of the device that performed the operation. These bits are invalid for targets that are selected under the single initiator option of the SCSI-1 specification.
  • Page 94 Read Only Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the LSI53C810A stacks interrupts). The DIP bit 5-20 Operating Registers...
  • Page 95 MDPE Master Data Parity Error This bit is set when the LSI53C810A as a master detects a data parity error, or a target device signals a parity error during a data phase. This bit is completely disabled by the Master Parity Error Enable bit (bit 3 of (CTEST4)).
  • Page 96 Operating Registers Reserved Illegal Instruction Detected This status bit is set any time an illegal instruction is detected, whether the LSI53C810A is operating in single step mode or automatically executing SCSI SCRIPTS. Any of the following conditions during instruction execution also set this bit:...
  • Page 97 Arbitration in Progress Arbitration in Progress (AIP = 1) indicates that the LSI53C810A has detected a Bus Free condition, asserted BSY, and asserted its SCSI ID onto the SCSI bus. Lost Arbitration When set, LOA indicates that the LSI53C810A has...
  • Page 98 FIFO Flags These four bits define the number of bytes that currently reside in the LSI53C810A’s SCSI synchronous data FIFO. These bits are not latched and they will change as data moves through the FIFO. The FIFO can hold up to 9 bytes.
  • Page 99 SCSI device selects or reselects the LSI53C810A. If the Connected bit is asserted and the LDSC bit is asserted, a disconnect is indicated. This bit is set when the Connected bit in (SCNTL1) is cleared.
  • Page 100 Interrupt Status (ISTAT) Read/Write ABRT This register is accessible by the host CPU while a LSI53C810A is executing SCRIPTS (without interfering in the operation of the function). It is used to poll for interrupts if hardware interrupts are disabled. Read this register after servicing an interrupt to check for stacked interrupts.
  • Page 101 The SCRIPTS processor may set this bit using a SCRIPTS register write instruction. An external processor may also set it while the LSI53C810A is executing a SCRIPTS operation. This bit enables the LSI53C810A to notify an external processor of a predefined condition while SCRIPTS are running.
  • Page 102 LSI53C810A responds to a bus-initiated selection or reselection. It is also set after the LSI53C810A wins arbitration when operating in low level mode. When this bit is clear, the LSI53C810A is not connected to the SCSI bus. Interrupt-on-the-Fly This bit is asserted by an INTFLY instruction during SCRIPTS execution.
  • Page 103 SCSI Interrupt Status One (SIST1) DMA Interrupt Pending This status bit is set when an interrupt condition is detected in the DMA portion of the LSI53C810A. The following conditions cause a DMA interrupt to occur: A PCI parity error is detected...
  • Page 104 Register: 0x19 (0x99) Chip Test One (CTEST1) Read Only FMT[3:0] FFL[3:0] Register: 0x1A (0x9A) Chip Test Two (CTEST2) Read Only DDIR DDIR 5-30 Operating Registers FMT[3:0] Byte Empty in DMA FIFO These bits identify the bottom bytes in the DMA FIFO that are empty.
  • Page 105 This bit indicates the status of the LSI53C810A’s internal TEOP signal. The TEOP signal acknowledges the completion of a transfer through the SCSI portion of the LSI53C810A. When this bit is set, TEOP is active. When this bit is clear, TEOP is inactive. DREQ Data Request Status This bit indicates the status of the LSI53C810A’s internal...
  • Page 106 When this bit is set, all data pointers for the DMA FIFO are cleared. Any data in the FIFO is lost. After the LSI53C810A successfully clears the appropriate FIFO points and registers, this bit automatically clears. This bit does not clear the data visible at the bottom of the FIFO.
  • Page 107 Return instruction is executed. This address points to the next instruction to execute. Do not write to this register while the LSI53C810A is executing SCRIPTS. During any Memory-to-Memory Move operation, the contents of this register are preserved. The power-up value of this register is indeterminate.
  • Page 108 Chapter 2, “Functional Description.” ZMOD SRTM Burst Disable When set, this bit causes the LSI53C810A to perform back-to-back cycles for all transfers. When this bit is cleared, back-to-back transfers for opcode fetches and burst transfers for data moves are performed. The...
  • Page 109 Setting this bit causes the LSI53C810A to place all output and bidirectional pins into a high impedance state. In order to read data out of the LSI53C810A, clear this bit. This bit is intended for board-level testing only. Do not set this bit during normal system operation.
  • Page 110 FBL[2:0] Register: 0x22 (0xA2) Chip Test Five (CTEST5) Read/Write ADCK ADCK BBCK 5-36 Operating Registers FIFO Byte Control FBL2 FBL1 FBL0 These bits steer the contents of the (CTEST6) register to the appropriate byte lane of the 32-bit DMA FIFO. If the FBL2 bit is set, then FBL1 and FBL0 determine which of four byte lanes can be read or written.
  • Page 111 contents and the current DNAD value. This bit automatically clears itself after decrementing the Byte Counter (DBC) Reserved MASR Master Control for Set or Reset Pulses This bit controls the operation of bit 3. When this bit is set, bit 3 asserts the corresponding signals. When this bit is cleared, bit 3 deasserts the corresponding signals.
  • Page 112 0xFFFFFF. If the instruction is a Block Move and a value of 0x000000 is loaded into the DMA Byte Counter (DBC) interrupt occurs if the LSI53C810A is not in target mode, Command phase. DMA Byte Counter (DBC) hold the least significant 24 bits of the first Dword of a SCRIPTS fetch, and to hold the offset value during table indirect I/O SCRIPTS.
  • Page 113 Read/Write DCMD DMA Command This 8-bit register determines the instruction for the LSI53C810A to execute. This register has a different format for each instruction. For a complete description, Chapter 6, “Instruction Set of the I/O Processor.” DNAD DMA Next Address This 32-bit register contains the general purpose address pointer.
  • Page 114 Registers: 0x30–0x33 (0xB0–0xB3) DMA SCRIPTS Pointer Save (DSPS) Read/Write DSPS 5-40 Operating Registers the first SCRIPTS instruction is written to this register, SCRIPTS instructions are automatically fetched and executed until an interrupt condition occurs. In single step mode, there is a single step interrupt after each instruction is executed.
  • Page 115 The LSI53C810A asserts the Bus Request (REQ/) output when the DMA FIFO can accommodate a transfer of at least one burst size of data. Bus Request (REQ/) is...
  • Page 116 I/O space; and if cleared, then the source address is in memory space. This function is useful for register-to-memory operations using the Memory Move instruction when the LSI53C810A is I/O mapped. Bits 4 and 5 of the Two (CTEST2) register are used to determine the configuration status of the LSI53C810A.
  • Page 117 PCI bus after certain conditions have been met. These conditions are described in Functional Description.” Burst Opcode Fetch Enable Setting this bit causes the LSI53C810A to fetch instructions in burst mode, if the Burst Disable bit Test Four (CTEST4), bit7) is cleared. Specifically, the chip bursts in the first two Dwords of all instructions using a...
  • Page 118 Register: 0x39 (0xB9) DMA Interrupt Enable (DIEN) Read/Write This register contains the interrupt mask bits corresponding to the interrupting conditions described in the interrupt is masked by clearing the appropriate mask bit. Masking an interrupt prevents IRQ/ from being asserted for the corresponding interrupt, but the status bit is still set in the Masking an interrupt does not prevent setting the ISTAT DIP.
  • Page 119 CLSE PFEN CLSE Cache Line Size Enable Setting this bit enables the LSI53C810A to sense and react to cache line boundaries set up by the (DMODE) or PCI Cache Line Size register, whichever contains the smaller value. Clearing this bit disables the...
  • Page 120 Start DMA bit needs to be set to start instruction fetches. This bit remains set until an interrupt occurs. When the LSI53C810A is in single step mode, set the Start DMA bit to restart execution of SCRIPTS after a single step interrupt.
  • Page 121 (ISTAT), this register cannot be accessed except by a SCRIPTS instruction during SCRIPTS execution. LSI53C700 Family Compatibility When this bit is cleared, the LSI53C810A behaves in a manner compatible with the LSI53C700 family; selection/reselection IDs are stored in both the Selector ID (SSID) registers.
  • Page 122 Function Complete Indicates full arbitration and selection sequence is completed. Selected Indicates the LSI53C810A is selected by a SCSI target device. Set the Enable Response to Selection bit in the SCSI Chip ID (SCID) Reselected Indicates the LSI53C810A is reselected by a SCSI initiator device.
  • Page 123 Any disconnect in low level mode causes this condition. SCSI Reset Condition This bit controls whether an interrupt occurs when the SRST/ signal is asserted by the LSI53C810A or any other SCSI device. Note that this condition is edge-triggered, so that multiple interrupts cannot occur because of a single SRST/ pulse.
  • Page 124 Reserved Selection or Reselection Time-out This bit controls whether an interrupt occurs when the SCSI device which the LSI53C810A was attempting to select or reselect did not respond within the programmed time-out period. See the description of the Zero (STIME0) register bits [3:0] for more information on the time-out timer.
  • Page 125 Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending (the LSI53C810A stacks interrupts). SCSI interrupt conditions may be individually masked through the...
  • Page 126 FIFO. Unexpected Disconnect This bit is set when the LSI53C810A is operating in the initiator mode and the target device unexpectedly disconnects from the SCSI bus. This bit is only valid register (and register must hold the chip’s...
  • Page 127 STO interrupt, since this is not considered an expected disconnect). SCSI RST/ Received This bit is set when the LSI53C810A detects an active SRST/ signal, whether the reset was generated external to the chip or caused by the Assert SRST/ bit in the...
  • Page 128 5-54 Operating Registers Reserved Selection or Reselection Time-out When the SCSI device which the LSI53C810A is attempting to select or reselect does not respond within the programmed time-out period. See the description of SCSI Timer Zero (STIME0) more information on the time-out timer.
  • Page 129 Data Bytes – 00000000 1. 11001100 11001100 (XOR of word 1) 2. 01010101 10011001 (XOR of word 1 and 2) 3. 00001111 10010110 (XOR of word 1, 2 and 3) Even parity >>> 10010110 4. 10010110 00000000 A one in any bit position of the final Parity (SLPAR) SCSI Longitudinal Parity (SLPAR) used to generate the check bytes for SCSI send...
  • Page 130 PSCPT SCPTS Register: 0x47 (0xC7) General Purpose Pin Control (GPCNTL) Read/Write This register is used to determine if the pins controlled by the Purpose (GPREG) Purpose Pin Control (GPCNTL) Purpose (GPREG) internal pull-up is also enabled. 5-56 Operating Registers When bits 3 through 0 are set, the corresponding access is considered local and the MAC/_TESTOUT pin is driven high.
  • Page 131 Fetch Enable The internal opcode fetch signal is presented on GPIO0 if this bit is set, regardless of the state of bit 0 (GPIO0_EN). Reserved GPIO_EN[1:0] GPIO Enable These bits power up set, causing the GPIO1 and GPIO0 pins to become inputs. Resetting these bits causes GPIO[1:0] to become outputs.
  • Page 132 Register: 0x49 (0xC9) SCSI Timer One (STIME1) Read/Write GEN[3:0] 5-58 Operating Registers HTH[7:4], SEL[3:0], Minimum Timeout GEN[3:0] (40 MHz) 0110 0111 1000 16 ms 1001 32 ms 1010 64 ms 1011 128 ms 1100 256 ms 1101 512 ms 1110 1.024 s 1111 2.048 s...
  • Page 133 GEN bit in the is set. Refer to the table under (STIME0), bits [3:0], for the available time-out periods. Note: To reset a timer before it expires and obtain repeatable delays, the time value must be written to zero first, and then written back to the desired value.
  • Page 134 ID, the “selected as” ID is written into these bits. Selection Response Logic Test This bit is set when the LSI53C810A is ready to be selected or reselected. This does not take into account the bus settle delay of 400 ns. This bit is used for functional test and fault purposes.
  • Page 135 It is used in low level synchronous SCSI operations. When this bit is set, the LSI53C810A, as a target, is waiting for the initiator to acknowledge the data transfers. If the LSI53C810A is an initiator, then the target has sent the offset number of requests.
  • Page 136 SCSI Output Control Latch (SOCL) SCSI Output Data Latch (SODL) of whether the LSI53C810A is configured as a target or initiator. Do not set this bit during normal operation, since it could cause contention on the SCSI bus. It is included for diagnostic purposes only.
  • Page 137 5 megatransfers per second) operations, because a valid assertion could be treated as a glitch. SCSI Low level Mode Setting this bit places the LSI53C810A in low level mode. In this mode, no DMA operations occur, and no SCRIPTS execute. Arbitration and selection may be performed by...
  • Page 138 I mode. Disable Single Initiator Response If this bit is set, the LSI53C810A ignores all bus-initiated selection attempts that employ the single initiator option from SCSI-1. In order to select the LSI53C810A while this bit is set, the LSI53C810A’s SCSI ID and the initiator’s SCSI ID must both be asserted.
  • Page 139 SCSI bus can be read from this register. Data can be written to the Latch (SODL) LSI53C810A by reading this register to allow loopback testing. When receiving SCSI data, the data flows into this register and out to the host FIFO. This register differs...
  • Page 140 Registers: 0x54 (0xD4) SCSI Output Data Latch (SODL) Read/Write SODL Registers: 0x58 (0xD8) SCSI Bus Data Lines (SBDL) Read Only SBDL 5-66 Operating Registers SODL SCSI Output Data Latch This register is used primarily for diagnostic testing or programmed I/O operation. Data written to this register is asserted onto the SCSI data bus by setting the Assert Data Bus bit in the SCSI Control One (SCNTL1)

  • Page 141: Low Level Register Interface Mode

    Section 6.6, “Transfer Control Instructions” Section 6.7, “Memory Move Instructions” Section 6.8, “Load and Store Instructions” After power-up and initialization, the LSI53C810A can be operated in the low level register interface mode or using SCSI SCRIPTS. 6.1 Low Level Register Interface Mode With the low level register interface mode, the user has access to the DMA control logic and the SCSI bus control logic.

  • Page 142: Scsi Scripts

    6.2 SCSI SCRIPTS To operate in the SCSI SCRIPTS mode, the LSI53C810A requires only a SCRIPTS start address. The start address must be at a Dword (four byte) boundary. This aligns subsequent SCRIPTS at a Dword boundary since all SCRIPTS are 8 or 12 bytes long. All instructions are fetched from external memory.

  • Page 143: Block Move Instructions

    SCSI SCRIPTS program for execution. Loading the LSI53C810A to request use of the PCI bus to fetch its first instruction from main memory at the address just loaded. SCSI SCRIPTS SCRIPTS Instructions...
  • Page 144 LSI53C810A requests use of the PCI bus again to transfer the data. When the LSI53C810A is granted the PCI bus, it executes (as a bus master) a burst transfer (programmable size) of data, decrements the internally stored remaining byte count, increments the address pointer, and then releases the PCI bus.

  • Page 145: Scripts Overview

    Status Buffer 6.3 Block Move Instructions The Block Move SCRIPTS instruction is used to move data between the SCSI bus and memory. For a Block Move instruction, the LSI53C810A operates much like a chaining DMA device with a SCSI controller attached.

  • Page 146: Second Dword

    6.3.1 First Dword IT[1:0] Instruction Set of the I/O Processor Instruction Type - Block Move Indirect Addressing When this bit is cleared, user data is moved to or from the 32-bit data start address for the Block Move instruction. The value is loaded into the chip’s address register and incremented as data is transferred.
  • Page 147 Note: Do not use indirect and table indirect addressing simultaneously; use only one addressing method at a time. Table Indirect Addressing When this bit is set, the 24-bit signed value in the start address of the move is treated as a relative displacement from the value in the register.

  • Page 148: Block Move Instruction Register

    For a MOVE instruction, the 24-bit byte count is fetched from system memory. Then the 32-bit physical address is brought into the LSI53C810A. Execution of the move begins at this point. Data Structure Address...
  • Page 149 MOVE Reserved These instructions perform the following steps: 1. The LSI53C810A verifies that it is connected to the SCSI bus as a Target before executing this instruction. 2. The LSI53C810A asserts the SCSI phase signals (SMSG/, SC_D/, and SI_O/) as defined by the Phase Field bits in the instruction.
  • Page 150 Instruction Defined Reserved MOVE These instructions perform the following steps: 1. The LSI53C810A verifies that it is connected to the SCSI bus as an Initiator before executing this instruction. 2. The LSI53C810A waits for an unserviced phase to occur. An unserviced phase is any phase (with SREQ/ asserted) for which the LSI53C810A has not yet transferred data by responding with a SACK/.

  • Page 151: I/O Instruction

    LSI53C810A deasserts SATN/ during the final SREQ/SACK/ handshake of the first move of Message-Out bytes after SATN/ was set. 7. When the LSI53C810A is performing a block move for Message-In phase, it does not deassert the SACK/ signal for the last SREQ/SACK/ handshake. Clear the SACK/ signal using the Clear SACK I/O instruction.

  • Page 152: Second Dword

    This 32-bit field specifies the starting address of the data to be moved to/from memory. This field is copied to the DMA Next Address (DNAD) LSI53C810A transfers data to or from memory, the Next Address (DNAD) register is incremented by the number of bytes transferred.

  • Page 153: Read/Write Instructions

    6.4 I/O Instruction The I/O SCRIPTS instruction causes the LSI53C810A to trigger common SCSI hardware sequences such as Set/Clear ACK, Set/Clear ATN, Set/Clear Target Mode, Select With ATN, or Wait for Reselect. 6.4.1 First Dword IT[1:0] OPC[2:0] Note: I/O Instruction indirect addressing, the value in this field is an offset into...
  • Page 154 32-bit jump address field stored in the DMA Next Address (DNAD) Manually set the LSI53C810A to Initiator mode if it is reselected, or to Target mode if it is selected. Disconnect Instruction The LSI53C810A disconnects from the SCSI bus by deasserting all SCSI signal outputs.
  • Page 155 Wait Select Instruction 1. If the LSI53C810A is selected, it fetches the next instruction from the address pointed to by the SCRIPTS Pointer (DSP) 2. If reselected, the LSI53C810A fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the...

  • Page 156: I/O Instruction Register

    Figure 6.3 instruction. Figure 6.3 I/O Instruction Register DCMD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Select with ATN/ Table Indirect Mode Relative Address Mode...
  • Page 157 Initiator Mode OPC2 OPC1 Select Instruction 1. The LSI53C810A arbitrates for the SCSI bus by asserting the SCSI ID stored in the (SCID) register. If it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status.
  • Page 158 Instruction Set of the I/O Processor field stored in the DMA Next Address (DNAD) Manually set the LSI53C810A to Initiator mode if it is reselected, or to Target mode if it is selected. 4. If the Select with SATN/ field is set, the SATN/ signal is asserted during the selection phase.
  • Page 159 Clear Instruction When the SACK/or SATN/ bits are cleared, the corresponding bits are cleared in the trol Latch (SOCL) the corresponding bit in the register is cleared. When the Carry bit is cleared, the corresponding bit in the ALU is cleared. Relative Addressing Mode When this bit is set, the 24-bit signed value in the Next Address (DNAD)
  • Page 160 6-20 Instruction Set of the I/O Processor An I/O command structure must have all four bytes contiguous in system memory, as shown below. The offset/period bits are ordered as in the (SXFER) register. The configuration bits are ordered as in the SCSI Control Three (SCNTL3) Config Use this bit only in conjunction with the Select, Reselect,...
  • Page 161 Set/Clear Target Mode This bit is used in conjunction with a Set or Clear instruction to set or clear Target mode. Setting this bit with a Set instruction configures the LSI53C810A as a target device (this sets bit 0 of the (SCNTL0) register).
  • Page 162 SACK/ and/or SATN/ on the SCSI bus. Since SACK/ and SATN/ are Initiator signals, they are not asserted on the SCSI bus unless the LSI53C810A is operating as an Initiator or the SCSI Loopback Enable bit is set in the...

  • Page 163: Read/Write Instructions

    It is possible to change register values from SCRIPTS in read-modify-write cycles or move to/from SFBR cycles. A[6:0] select an 8-bit source/destination register within the LSI53C810A. Destination Address This field contains the 32-bit destination address where the data is to move.

  • Page 164: Move To/From Sfbr Cycles

    The Add operation is used to increment or decrement register values (or memory values if used in conjunction with a Memory-to-Register Move operation) for use as loop counters. 6.5.4 Move To/From SFBR Cycles All operations are read-modify-writes. However, two registers are involved, one of which is always the SFBR.

  • Page 165: Read/Write Register Instruction

    Figure 6.4 instruction. Figure 6.4 Read/Write Register Instruction DCMD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 (Reserved) Operator 0 Operator 1...

  • Page 166: Read/Write Instructions

    Table 6.2 Read/Write Instructions Opcode 111 Operator Read-Modify-Write Move data into register. Syntax: “Move data8 to RegA” Shift register one bit to the left and place the result in the same register. Syntax: “Move RegA SHL RegA” OR data with register and place the result in the same register.

  • Page 167: Transfer Control Instructions

    Table 6.2 Read/Write Instructions Opcode 111 Operator Read-Modify-Write Add data to register without carry and place the result in the same register. Syntax: “Move RegA + data8 to RegA” Add data to register with carry and place the result in the same register. Syntax: “Move RegA + data8 to RegA with carry”...
  • Page 168 OPC2 OPC1 OPC0 Jump Instruction The LSI53C810A can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as defined by the Phase Compare, Data Compare and True/False bit fields. If the comparisons are true, then it loads the...
  • Page 169 If the comparisons are false, the LSI53C810A fetches the next instruction from the address pointed to by the SCRIPTS Pointer (DSP) pointer is not modified. Return Instruction The LSI53C810A can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as defined by the Phase Compare, Data Compare, and...

  • Page 170: Transfer Control Instruction

    Figure 6.5 Control instruction. Figure 6.5 Transfer Control Instruction DCMD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Relative Addressing Mode Opcode Bit 0 Opcode Bit 1...
  • Page 171 If the comparisons are false, the LSI53C810A fetches the next instruction from the address pointed to by the SCRIPTS Pointer (DSP) pointer is not modified. Interrupt Instruction The LSI53C810A can do a true/false comparison of the ALU carry bit, or compare the phase and/or data as defined by the Phase Compare, Data Compare, and...
  • Page 172 The SCRIPTS program counter is a 32-bit value pointing to the SCRIPTS instruction currently under execution by the LSI53C810A. The next address is formed by adding the 32-bit program counter to the 24-bit signed value of the last 24 bits of the Jump or Call instruction. Because it is signed (2’s complement), the jump can be forward or...
  • Page 173 Interrupt-on-the-Fly bit asserted. Jump If True/False This bit determines whether the LSI53C810A branches when a comparison is true or when a comparison is false. This bit applies to phase compares, data compares, and carry tests. If both the Phase Compare and Data Compare bits are set, then both compares must be true to branch on a true condition.
  • Page 174 SCSI SATN/ signal. Wait For Valid Phase If the Wait for Valid Phase bit is set, the LSI53C810A waits for a previously unserviced phase before comparing the SCSI phase and data.
  • Page 175 This 32-bit field contains the address of the next instruction to fetch when a jump is taken. Once the LSI53C810A has fetched the instruction from the address pointed to by these 32 bits, this address is incremented by 4, loaded into the DMA SCRIPTS Pointer (DSP) register and becomes the current instruction pointer.

  • Page 176: Memory Move Instructions

    This SCRIPTS instruction allows the LSI53C810A to execute high-performance block moves of 32-bit data from one part of main memory to another. In this mode, the LSI53C810A is an independent, high-performance DMA controller irrespective of SCSI operations. Since the registers of the LSI53C810A can be mapped into system memory, this SCRIPTS instruction also moves an LSI53C810A register to or from memory or another LSI53C810A register.

  • Page 177: Memory To Memory Move Instruction

    Figure 6.6 Move instruction. Figure 6.6 Memory to Memory Move Instruction DCMD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 No Flush 0 (Reserved) 0 (Reserved)

  • Page 178: Third Dword

    These bits are reserved and must be zero. If any of these bits is set, an illegal instruction interrupt occurs. No Flush When this bit is set, the LSI53C810A performs a Memory Move (MMOV) without flushing the prefetch unit (NFMMOV). When this bit is cleared, the Memory Move instruction automatically flushes the prefetch unit.

  • Page 179: Load And Store Instructions

    Memory Move. However, it can be loaded using SCRIPTS Read/Write operations. To load the SFBR with a byte stored in system memory, first move the btye to an intermediate LSI53C810A register (for example, a SCRATCH register), and then to the SFBR.
  • Page 180 Data Structure Address Reserved No Flush (Store instruction only) When this bit is set, the LSI53C810A performs a Store without flushing the prefetch unit. When this bit is cleared, the Store instruction automatically flushes the prefetch unit. Use No Flush if the source and destination are not within four instructions of the current Store instruction.
  • Page 181 When this bit is set, the instruction is a Load. When cleared, it is a Store. Reserved Register Address A[6:0] select the register to Load and Store to/from within the LSI53C810A. It is not possible to load the (SFBR) register, although the SFBR contents may be stored in another location.

  • Page 182: Load And Store Instruction Format

    Figure 6.7 Store instruction. Figure 6.7 Load and Store Instruction Format DCMD Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 (Reserved) Load/Store No Flush...

  • Page 183: Pci Interface Timing Diagrams

    Section 7.4, “PCI Interface Timing Diagrams” Section 7.5, “PCI Interface Timing” Section 7.6, “SCSI Timings” Section 7.7, “Package Drawings” 7.1 DC Characteristics This section of the manual describes the LSI53C810A DC characteristics. specifications. LSI53C810A PCI to SCSI I/O Processor Table 7.1 through Table 7.11...
  • Page 184 Table 7.1 Absolute Maximum Stress Ratings Symbol Parameter Storage temperature Supply voltage Input voltage Latch-up current Electrostatic discharge 2 V < V < 8 V. 2. SCSI pins only. Note: Stresses beyond those listed above may cause permanent damage to the device. These are stress ratings only;...

  • Page 185: Scsi Signals-Smsg, Si_O/, Sc_D/, Satn/, Sbsy/, Ssel/, Srst

    Table 7.3 SCSI Signals—SD[7:0]/, SDP/, SREQ/, SACK/ Symbol Parameter Input high voltage Input low voltage Output high voltage Output low voltage Input leakage 3-state leakage 1. TolerANT active negation enabled. Table 7.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/ Symbol Parameter Input high voltage...

  • Page 186: Capacitance

    Table 7.6 Capacitance Symbol Parameter Input capacitance of input pads Input capacitance of I/O pads Table 7.7 Output Signals—MAC/_TESTOUT, REQ/ Symbol Parameter Output high voltage Output low voltage Output high current Output low current 3-state leakage Note: REQ/ has a 100 A pull-up that is enabled when TESTIN is low. Table 7.8 Output Signal—IRQ/ Symbol...

  • Page 187: Irdy/, Trdy/, Devsel/, Stop/, Perr/, Par/

    Table 7.9 Output Signal—SERR/ Symbol Parameter Output low voltage Output low current 3-state leakage Table 7.10 Bidirectional Signals—AD[31:0], C_BE/[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR/ Symbol Parameter Input high voltage Input low voltage Output high voltage Output low voltage Output high current Note: All the signals in this table have 100 A pull-ups that are enabled when TESTIN is low.

  • Page 188: Bidirectional Signals—Gpio0_Fetch Gpio1_Master/

    Note: All the signals in this table have 100 A pull-ups that are enabled when TESTIN is low. 7.2 TolerANT Technology The LSI53C810A features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers.

  • Page 189: Tolerant Technology Electrical Characteristics

    Table 7.12 TolerANT Technology Electrical Characteristics Symbol Parameter Output high voltage Output low voltage Input high voltage Input low voltage Input clamp voltage Threshold, HIGH to LOW Threshold, LOW to HIGH –V Hysteresis Output high current Output low current Short-circuit output high current Short-circuit output low current Input high leakage Input low leakage...

  • Page 190: Rise And Fall Time Test Conditions

    Figure 7.1 Figure 7.2 SCSI Input Filtering REQ/ or ACK/ Input Note: t is the input filtering period. Figure 7.3 Electrical Characteristics Rise and Fall Time Test Conditions 20 pF 2.5 V Hysteresis of SCSI Receiver Input Voltage (Volts)

  • Page 191: Output Current As A Function Of Output Voltage

    Figure 7.4 Figure 7.5 Output Current as a Function of Output Voltage Output Voltage (Volts) TolerANT Technology Input Current as a Function of Input Voltage 8.2 V 0.7 V OUTPUT ACTIVE Input Voltage (Volts) 14.4 V HIGH-Z Output Voltage (Volts)

  • Page 192: Clock Timing

    7.3 AC Characteristics The AC characteristics described in this section apply over the entire range of operating conditions (refer to Chip timings are based on simulation at worst case voltage, temperature, and processing. Timings were developed with a load capacitance of 50 pF.

  • Page 193: Reset Input Timing

    Table 7.14 Table 7.14 Reset Input Timing Symbol Parameter Reset pulse width Reset deasserted setup to CLK HIGH Figure 7.7 Reset Input RST/ 1. When enabled. Table 7.15 Table 7.15 Interrupt Output Symbol Parameter CLK HIGH to IRQ/ LOW CLK HIGH to IRQ/ HIGH IRQ/ deassertion time Figure 7.8 IRQ/...

  • Page 194: Pci Interface Timing Diagrams

    7.4 PCI Interface Timing Diagrams Figure 7.9 LSI53C810A accesses the PCI bus. The timings for the PCI bus interface are listed on this section: Target Timing PCI Configuration Register Read PCI Configuration Register Write Target Read Target Write Initiator Timing...

  • Page 195: Pci Configuration Register Read

    (Driven by System) (Driven by Master-Addr; LSI53C810A-Data) C_BE/ (Driven by Master) (Driven by Master-Addr; LSI53C810A-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C810A) STOP/ (Driven by LSI53C810A) DEVSEL/ (Driven by LSI53C810A) IDSEL (Driven by Master) PCI Interface Timing Diagrams through Figure 7.12 describe target timing.

  • Page 196: Pci Configuration Register Write

    FRAME/ (Driven by Master) (Driven by Master) C_BE/ (Driven by Master) PAR/ (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C810A) STOP/ (Driven by LSI53C810A) DEVSEL/ (Driven by LSI53C810A) IDSEL (Driven by Master) 7-14 Electrical Characteristics Addr Data In...

  • Page 197: Target Read

    (Driven by Master) Addr (Driven by Master-Addr; LSI53C810A-Data) C_BE/ (Driven by Master) (Driven by Master-Addr; LSI53C810A-Data) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C810A) STOP/ (Driven by LSI53C810A) DEVSEL/ (Driven by LSI53C810A) PCI Interface Timing Diagrams Byte Enable Data 7-15...

  • Page 198: Target Write

    (Driven by System) FRAME/ (Driven by Master) Addr (Driven by Master) C_BE/ (Driven by Master) PAR/ (Driven by Master) IRDY/ (Driven by Master) TRDY/ (Driven by LSI53C810A) STOP/ (Driven by LSI53C810A) DEVSEL/ (Driven by LSI53C810A) 7-16 Electrical Characteristics Data In Byte Enable...

  • Page 199: Opcode Fetch, Nonburst

    7.4.2 Initiator Timing Figure 7.13 Figure 7.13 OpCode Fetch, Nonburst (Driven by System) GPIO0_FETCH/ (Driven by LSI53C810A) GPIO1_MASTER/ (Driven by LSI53C810A) REQ/ (Driven by LSI53C810A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C810A) (Driven by LSI53C810A- Addr; Target-Data) C_BE/ (Driven by LSI53C810A)

  • Page 200: Burst Opcode Fetch

    Figure 7.14 Burst Opcode Fetch (Driven by System) GPIO0_FETCH/ (Driven by LSI53C810A) GPIO1_MASTER/ (Driven by LSI53C810A) REQ/ (Driven by LSI53C810A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C810A) (Driven by LSI53C810A- Addr; Target-Data) C_BE/ (Driven by LSI53C810A) (Driven by LSI53C810A- Addr;...

  • Page 201: Back-To-Back Read

    Figure 7.15 Back-to-Back Read (Driven by System) GPIO0_FETCH/ (Driven by LSI53C810A GPIO1_MASTER/ (Driven by LSI53C810A) REQ/ (Driven by LSI53C810A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C810A) (Driven by LSI53C810A- Addr; Target-Data) C_BE/ (Driven by LSI53C810A) (Driven by LSI53C810A- Addr; Target-Data...

  • Page 202: Back-To-Back Write

    Figure 7.16 Back-to-Back Write (Driven by System) GPIO0_FETCH/ (Driven by LSI53C810A) GPIO1_MASTER/ (Driven by LSI53C810A) REQ/ (Driven by LSI53C810A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C810A) (Driven by LSI53C810A) C_BE/ (Driven by LSI53C810A) PAR/ (Driven by LSI53C810A) IRDY/ (Driven by LSI53C810A)
  • Page 203 This page intentionally left blank. PCI Interface Timing Diagrams 7-21...

  • Page 204: Burst Read

    Figure 7.17 Burst Read GPIO0_FETCH/ (Driven by LSI53C810A) GPIO1_MASTER/ (Driven by LSI53C810A) REQ/ (Driven by LSI53C810A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C810A) (Driven by LSI53C810A- Addr; Target-Data) C_BE/ (Driven by LSI53C810A) (Driven by LSI53C810A- Addr; Target-Data) IRDY/ (Driven by LSI53C810A)
  • Page 205 Figure 7.17 Burst Read (Cont.) GPIO0_FETCH/ (Driven by LSI53C810A) GPIO1_MASTER/ (Driven by LSI53C810A) REQ/ (Driven by LSI53C810A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C810A) (Driven by LSI53C810A- Addr; Target-Data) C_BE/ (Driven by LSI53C810A) (Driven by LSI53C810A- Addr; Target-Data) IRDY/...

  • Page 206: Burst Write

    Figure 7.18 Burst Write (Driven by System) GPIO0_ FETCH/ (Driven by LSI53C810A) GPIO1_ MASTER/ (Driven by LSI53C810A) REQ/ (Driven by LSI53C810A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C810A) (Driven by LSI53C810A) C_BE/ (Driven by LSI53C810A) (Driven by LSI53C810A) IRDY/...
  • Page 207 Figure 7.18 Burst Write (Cont.) (Driven by System) GPIO0_ FETCH/ (Driven by LSI53C810A) GPIO1_ MASTER/ (Driven by LSI53C810A) REQ/ (Driven by LSI53C810A) GNT/ (Driven by Arbiter) FRAME/ (Driven by LSI53C810A) Data (Driven by LSI53C810A) C_BE/ (Driven by LSI53C810A) (Driven by LSI53C810A)

  • Page 208: Pci Timing

    CLK to side signal output valid CLK high to FETCH/ low CLK high to FETCH/ high CLK high to MASTER/ low CLK high to MASTER/ high 7-26 Electrical Characteristics describes the PCI timing data for the LSI53C810A. Unit – – – – –...

  • Page 209: Scsi Timings

    7.6 SCSI Timings Tables LSI53C810A SCSI timing data. Table 7.17 Initiator Asynchronous Send (5 Mbytes/s) Symbol Parameter SACK/ asserted from SREQ/ asserted SACK/ deasserted from SREQ/ deasserted Data setup to SACK/ asserted Data hold from SREQ/ deasserted Figure 7.19 Initiator Asynchronous Send...

  • Page 210: Initiator Asynchronous Receive

    Table 7.18 Initiator Asynchronous Receive (5 Mbytes/s) Symbol Parameter SACK/ asserted from SREQ/ asserted SACK/ deasserted from SREQ/ deasserted Data setup to SREQ/ asserted Data hold from SACK/ asserted Figure 7.20 Initiator Asynchronous Receive SREQ/ SACK/ SD[7:0], Valid n SDP/ 7-28 Electrical Characteristics Unit...

  • Page 211: Target Asynchronous Send

    Table 7.19 Target Asynchronous Send (5 Mbytes/s) Symbol Parameter SACK/ asserted from SREQ/ asserted SACK/ deasserted from SREQ/ deasserted Data setup to SREQ/ asserted Data hold from SACK/ asserted Figure 7.21 Target Asynchronous Send SREQ/ SACK/ SD[7:0], SDP/ SCSI Timings Valid n –...

  • Page 212: Target Asynchronous Receive

    Table 7.20 Target Asynchronous Receive (5 Mbytes/s) Symbol Parameter SREQ/ deasserted from SACK/ asserted SREQ/ asserted from SACK/ deasserted Data setup to SREQ/ asserted Data hold from SACK/ asserted Figure 7.22 Target Asynchronous Receive SREQ/ SACK/ SD[7:0], SDP/ Figure 7.23 Initiator and Target Synchronous Transfers SREQ/ or SACK/ Send Data...

  • Page 213: Scsi-2 Fast Transfers (10.0 Mbytes/S (8-Bit Transfers 40 Mhz Clock)

    Table 7.21 SCSI-1 Transfers (SE, 5.0 Mbytes/s) Symbol Parameter Send SREQ/ or SACK/ assertion pulse width Send SREQ/ or SACK/ deassertion pulse width Receive SREQ/ or SACK/ assertion pulse width Receive SREQ/ or SACK/ deassertion pulse width Send data setup to SREQ/ or SACK/ asserted Send data hold from SREQ/ or SACK/ asserted Receive data setup to SREQ/ or SACK/ asserted Receive data hold from SREQ/ or SACK/ asserted...

  • Page 214: Scsi-2 Fast Transfers (10.0 Mbytes/S (8-Bit Transfers 50 Mhz Clock)

    Table 7.23 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers), 50 MHz Clock) Symbol Parameter Send SREQ/ or SACK/ assertion pulse width Send SREQ/ or SACK/ deassertion pulse width Receive SREQ/ or SACK/ assertion pulse width Receive SREQ/ or SACK/deassertion pulse width Send data setup to SREQ/ or SACK/ asserted Send data hold from SREQ/ or SACK/ asserted Receive data setup to SREQ/ or SACK/ asserted...

  • Page 215: Package Drawings

    7.7 Package Drawings Figure 7.24 illustrates the mechanical drawing for the LSI53C810A. Package Drawings 7-33...

  • Page 216: Ld Pqfp (Ud) Mechanical Drawing (Sheet 1 Of 2)

    Figure 7.24 100 LD PQFP (UD) Mechanical Drawing (Sheet 1 of 2) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UD. 7-34...
  • Page 217 Figure 7.24 100 LD PQFP (UD) Mechanical Drawing (Sheet 2 of 2) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UD. Package Drawings...
  • Page 218 7-36 Electrical Characteristics...

  • Page 219: A.1 Configuration Registers

    Device ID Header Type Interrupt Line Interrupt Pin Latency Timer Max_Lat Min_Gnt Revision ID Status Vendor ID LSI53C810A PCI to SCSI I/O Processor lists the LSI53C810A configuration registers by register name. Address 0x14 0x10 0x0C 0x09 0x04 0x02 0x0E 0x3C 0x3D...

  • Page 220: A.2 Scsi Registers

    DMA Status (DSTAT) General Purpose (GPREG) General Purpose Pin Control (GPCNTL) Interrupt Status (ISTAT) Memory Access Control (MACNTL) Response ID (RESPID) Register Summary lists the LSI53C810A SCSI registers by register name. Address 0x3C–0x3F (0xBC–0xBF) 0x22 (0xA2) 0x21 (0xA1) 0x19 (0x99) 0x23 (0xA3)
  • Page 221 Table A.2 SCSI Registers Register Name Scratch Byte Register (SBR) Scratch Register A (SCRATCHA) SCSI Bus Control Lines (SBCL) SCSI Bus Data Lines (SBDL) SCSI Chip ID (SCID) SCSI Control One (SCNTL1) SCSI Control Three (SCNTL3) SCSI Control Two (SCNTL2) SCSI Control Zero (SCNTL0) SCSI Destination ID (SDID) SCSI First Byte Received (SFBR)
  • Page 222 Table A.2 SCSI Registers Register Name SCSI Test Two (STEST2) SCSI Test Zero (STEST0) SCSI Timer One (STIME1) SCSI Timer Zero (STIME0) SCSI Transfer (SXFER) Temporary (TEMP) Register Summary Address 0x4E (0xCE) 0x4C (0xCC) 0x49 (0xC9) 0x48 (0xC8) 0x05 (0x85) 0x1C–0x1F (0x9C–0x9F) Read/Write Page...
  • Page 223 SCSI data bus bit assert SCSI I_O/ bit 5-18 assert SCSI MSG/ bit 5-18 assert SCSI REQ/ signal bit 5-18 LSI53C810A PCI to SCSI I/O Processor assert SCSI RST/ signal bit assert SCSI SEL/ bit ATN bit 5-18 5-20 base address register...
  • Page 224 clock address incrementor bit 5-36 clock byte counter bit 5-36 clock conversion factor bits 5-10 CLSE bit 5-45 CM bit 5-31 CMP bit 5-48 5-51 COM bit 5-47 CON bit 5-28 configured as I/O bit 5-31 configured as memory bit 5-31 connected bit 5-28...
  • Page 225 6-39 no flush option 6-40 prefetch unit and store instructions lost arbitration bit 5-23 LOW bit 5-63 LSI53C700 family compatibility bit 5-47 LSI53C810A ease of use flexibility integration performance reliability testability Index M/A bit 5-48 MACNTL register...
  • Page 226 SCSI bus data lines 5-66 SCSI chip ID 5-11 SCSI control one register SCSI control register two SCSI control three SCSI control zero SCSI destination ID 5-15 SCSI first byte received 5-17 SCSI input data latch 5-65 SCSI interrupt enable one 5-50 SCSI interrupt enable zero 5-48...
  • Page 227 0x41 5-50 0x42 5-51 0x43 5-53 0x44 5-54 0x46 5-55 0x47 5-56 0x48 5-57 0x49 5-58 0x4A 5-59 0x4C 5-60 0x4D 5-61 0x4E 5-62 0x4F 5-63 0x50 5-65 0x54 5-66 0x58 5-66 PCI configuration registers 0x00 3-11 0x02 3-11 0x04 3-11 0x06 3-13...
  • Page 228 SCRIPTS interrupt instruction received SCSI C_D/ signal 5-25 SCSI control enable 5-62 SCSI data high impedance 5-35 SCSI disconnect unexpected SCSI FIFO test read 5-64 SCSI FIFO test write 5-65 SCSI gross error 5-48 5-52 SCSI high impedance mode 5-62 SCSI I_O/ signal 5-25 SCSI interrupt pending...
  • Page 229 SCSI I_O/ bit 5-25 SCSI input data latch register 5-65 SCSI instructions block move 6-13 load/store 6-39 memory move 6-36 read/write 6-23 SCSI interrupt enable one register 5-50 SCSI interrupt enable zero register 5-48 SCSI interrupt pending bit 5-28 SCSI interrupt status one register 5-53 SCSI interrupt status zero register 5-51...
  • Page 230 Storage Device Management System (SDMS) STR bit 5-64 STW bit 5-65 SXFER register 5-12 synchronous clock conversion factor bits synchronous data transfer rate 2-13 synchronous operation 2-13 SZM bit 5-62 target mode SATN/ active 5-51 target mode bit target ready TE bit 5-63 TEMP register...

  • Page 231: Customer Feedback

    Please include your name, phone number, fax number, and company address so that we may contact you directly for clarification or additional information. Thank you for your help in improving the quality of our documents. LSI53C810A PCI to SCSI I/O Processor...
  • Page 232 Reader’s Comments Fax your comments to: Please tell us how you rate this document: LSI53C810A PCI to SCSI I/O Processor Technical Manual. Place a check mark in the appropriate blank for each category. Completeness of information Clarity of information Ease of finding information...
  • Page 233 U.S. Distributors by State A. E. Avnet Electronics Colorado http://www.hh.avnet.com Denver B. M. Bell Microproducts, A. E. Inc. (for HAB’s) B. M. http://www.bellmicro.com W. E. I. E. Insight Electronics Englewood http://www.insight-electronics.com I. E. W. E. Wyle Electronics http://www.wyle.com Connecticut Cheshire Alabama A.
  • Page 234 U.S. Distributors by State (Continued) New York South Carolina Hauppauge A. E. I. E. Tel: 516.761.0960 W. E. Long Island South Dakota A. E. Tel: 516.434.7400 A. E. W. E. Tel: 800.861.9953 W. E. Rochester A. E. Tel: 716.475.9130 Tennessee I.
  • Page 235 Direct Sales Representatives by State (Component and Boards) E. A. Earle Associates Texas E. L. Electrodyne - UT Austin Group 2000 I. S. Infinity Sales, Inc. Arlington ION Associates, Inc. R. A. Rathsburg Associ- Houston ates, Inc. Synergy Associates, Utah Inc.
  • Page 236 Ottawa Tel: 613.592.1263 Kentucky Fax: 613.592.3253 Bowling Green Tel: 270.793.0010 Fax: 270.793.0040 INTERNATIONAL Taiwan Taipei France LSI Logic Asia, Inc. Paris Taiwan Branch LSI Logic S.A. Tel: 886.2.2718.7828 Immeuble Europa Fax: 886.2.2718.8869 Tel: 33.1.34.63.13.13 Fax: 33.1.34.63.13.19 United Kingdom Bracknell Germany...
  • Page 237 Fax: 86.10.6804.2521 Acal Nederland b.v. Tel: 31.40.2.502602 France Fax: 31.40.2.510255 Rungis Cedex Azzurri Technology France Switzerland Tel: 33.1.41806310 Brugg Fax: 33.1.41730340 LSI Logic Sulzer AG Tel: 41.32.3743232 Germany Fax: 41.32.3743233 Haar EBV Elektronik Taiwan Tel: 49.89.4600980 Taipei Fax: 49.89.46009840 Avnet-Mercuries...

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