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8-6
POC1_5
Power-On Configuration 1_5
The reset value of this bit matches the TTL voltage level
on the A13 pin on reset.
POC1_4
Power-On Configuration 1_4
The reset value of this bit matches the TTL voltage level
on the A12 pin on reset. If high, the download speed will
be increased to an SCL of 1250 kHz. This bit is for test
purposes only, and should remain clear for normal
operation.
DLSEL
Download Configuration Select
Chooses between the 2 two-wire serial ports for the initial
download. The reset value of this bit matches the TTL
voltage level on the A11 pin at reset. A value of 0 selects
two-wire serial port 0, a value of 1 selects two-wire serial
port 1.
DLADR[2:0]
Download ROM Address
The chip address of the serial ROM to be used in the
power-on download is defined by using pull-downs on the
A8, A9, and A10 pins. (See
Register: 0xFF04
LED Blink Rate (LBR)
Read/Write
7
6
R
0
0
Each of the LED output pins, controlled by the LED registers defined
later in this register block, can be programmed to be constantly on,
constantly off, or to blink at one of two different blink rates. The blink
rates for all LED pins are defined globally in this register.
System Registers
5
4
FBR1
FBR0
Defaults:
0
0
Chapter
2).
3
2
1
R
SBR1
0
0
0
5
4
3
[2:0]
0
SBR0
0
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