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Table 6.5
Schmitt Input Signals (REFCLK, TESTRESET/, ZCLK, TCK, TDI, TRST/,
TMS_CHIP, TMS_ICE)
Symbol
Parameter
V
Input high voltage
IH
V
Input low voltage
IL
I
Input leakage
IN
Table 6.6
4 mA Bidirectional Signals (LIPRESET/, ODIS1, ODIS0, BYPASS1/,
BYPASS0/, MD[31:0], MA[21:0], MWE[1:0]/, FLASHCS/, BWE[3:0]/,
RAMCS/, ZZ, MP[3:0], SCL, SDA, RXLOS1, RXLOS0, ADSC/, ADV/, TDO)
Symbol
Parameter
V
Input high voltage
IH
V
Input low voltage
IL
V
Output high voltage
OH
V
Output low voltage
OL
I
3-state leakage
OZ
Table 6.7
8 mA Bidirectional Signals (MODDEF1[2:0], MODDEF0[2:0], GPIO[3:0],
MOE[1:0]/, LED[4:0]/, MCLK)
Symbol
Parameter
V
Input high voltage
IH
V
Input low voltage
IL
V
Output high voltage
OH
V
Output low voltage
OL
I
3-state leakage
OZ
Electrical Requirements
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Min
Max
2.0
V
+ 0.3
DD
− 0.3
V
0.8
SS
10
10
Min
Max
0.7 V
V
+ 0.3
DD
DD
− 0.3
V
0.2 V
SS
DD
2.4
V
DD
V
0.4
SS
− 10
10
Min
Max
0.7 V
V
+ 0.3
DD
DD
− 0.3
V
0.2 V
SS
DD
2.4
V
DD
V
0.4
SS
− 10
10
Unit
Test Conditions
V
–
V
–
µA
–
Unit
Test Conditions
V
–
V
–
− 4 mA
V
V
4 mA
µA
–
Unit
Test Conditions
V
–
V
–
− 8 mA
V
V
8 mA
µA
–
6-3
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