Mitsubishi Electric MELSEC iQ-F FX5 User Manual page 442

Warning output flag (Rate alarm upper limit/lower limit) [FX2N allocation mode]
When the FX2N allocation mode function is used, the upper/lower limit alarm of the rate alarm can be checked.
b15 b14 b13 b12 b11 b10 b9
CH8 CH8 CH7 CH7 CH6
(1) 0: Normal, 1: Alarm ON
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Alert output flag (Rate alarm) (in FX2N allocation mode
function)
■Alert output flag status
• If the value is out of the range specified in the rate alarm upper limit value or the rate alarm lower limit value, Alarm ON (1)
is stored in Alert output flag (rate alarm) corresponding to each channel.
• If an alert is detected even in one channel, of the channels where conversion is enabled and the alert output setting
(Process alarm) is enabled, 'Alert output signal' (Un\G69, b8) also turns on.
■Clearing Alert output flag
• When the change rate of the digital output value falls within the rate alarm upper limit value or less, or rate alarm lower limit
value or more, the flag is automatically cleared.
• Turning offonoff 'Operating condition setting request' (Un\G70, b9) allows the flag to be cleared.
Input signal error detection flag
The status of an analog input value can be checked for each channel.
b15 b14 b13 b12 b11 b10 b9
0 0 0 0 0
(2)
(1) 0: Normal, 1: Input signal error
(2) The values of b8 to b15 are fixed to 0.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Input signal error detection flag
■Input signal error detection flag status
• When an analog input value out of the range specified in Input signal error detection setting value is detected, Input signal
error detection flag corresponding to each channel of detection turns to Input signal error (1).
• When an error is detected in any channel where the conversion and the input signal error detection are enabled, 'Input
signal error detection signal' (Un\G69, b12) turns on.
APPX
440
Appendix 12 Buffer Memory Areas
b8 b7 b6 b5 b4
CH6 CH5 CH5 CH4 CH4 CH3 CH3
(1)
b8 b7 b6 b5 b4
0 0 0 CH8 CH7 CH6 CH5
b3 b2 b1 b0
CH2 CH2 CH1 CH1
CH1 CH2 CH3
27
b3 b2 b1 b0
CH4 CH3 CH2 CH1
(1)
CH1 CH2 CH3
40
CH4 CH5 CH6
CH4 CH5 CH6
CH7 CH8
CH7 CH8