Mitsubishi Electric MELSEC iQ-F FX5 User Manual page 139

Condition target setting [n]
Set an interrupt factor to be detected.
Setting value Setting content
0 Disable
1 Error flag (Un\G69, b15)
2 Warning output flag (Process alarm)
3 Warning output flag (Rate alarm)
4 Input signal error detection flag
5 A/D conversion completed
6 Logging hold flag
7 Logging read
If a value other than the above is set, a condition target setting range error (error code: 181H) occurs.
When the buffer memory set to 'Condition target setting [n]' (Un\G232 to Un\G247) turns offon, an interrupt request is sent
to the CPU module.
"n" indicates an interrupt setting number. (n = 1 to 16)
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name 1
Condition target setting [n] 232
Condition target setting [n] (in 4081
FX3 allocation mode
function)
■Enabling the setting
Turn offonoff 'Operating condition setting request' (Un\G70, b9) to enable the setting.
■Default value
The default value is 0 for all channels.
Condition target channel setting [n]
Set a channel where an interrupt is detected.
Setting value
0
1
2
3
4
When a factor for the channel specification is set to 'Condition target setting [n]' (Un\G232 to Un\G247), an interrupt factor in
the channel set by this area is monitored.
If a value other than the above is set, a condition target setting range error (error code: 182H) occurs.
"n" indicates an interrupt setting number. (n = 1 to 16)
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name 1
Condition target channel 264
setting [n]
Condition target channel 4101
setting [n] (in FX3 allocation
mode function)
■Enabling the setting
Turn offonoff 'Operating condition setting request' (Un\G70, b9) to enable the setting.
2 3 4 5 6
233 234 235 236 237
4082 4083 4084 4085 4086
2 3 4 5 6
265 266 267 268 269
4102 4103 4104 4105 4106
7 8 9 10 11
238 239 240 241 242
4087 4088 4089 4090 4091
Setting content
All channels
CH1
CH2
CH3
CH4
7 8 9 10 11
270 271 272 273 274
4107 4108 4109 4110 4111
Appendix 4 Buffer Memory Areas
12 13 14 15 16
243 244 245 246 247
4092 4093 4094 4095 4096
12 13 14 15 16
275 276 277 278 279
4112 4113 4114 4115 4116
APPX
137
A