Mitsubishi Electric MELSEC iQ-F FX5 User Manual page 141

Input signal error detect automatic clear enable/disable setting
Set whether to enable or disable automatic clearing of input signal errors by using the input signal error detection function.
Setting value
0
1
Setting a value other than in the table above results in operation with Disable (1).
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Input signal error detect automatic clear enable/
disable setting
Input signal error detect automatic clear enable/
disable setting (in FX3 allocation mode function)
■Enabling the setting
Turn offonoff 'Operating condition setting request' (Un\G70, b9) to enable the setting.
■Default value
The default value is Disable (1).
Offset/gain initialization enable code
When the offset/gain initialization request (Un/G70, b5) turns offon by setting the enable code "E20FH" in this area at the
time of initialization of offset/gain, the offset value and the gain value in the flash memory of the analog input module are
initialized.
When setting anything other than "E20FH" in this area, initialization is not executed.
When Offset/gain initialization is completed, the values are initialized to "0000H".
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Offset/gain initialization enable code
Offset/gain initialization enable code (In FX3
allocation mode function)
■Default value
The default value is set to 0.
CH1 Digital output value
The A/D-converted digital output value is stored in 16-bit signed binary value.
b15 b14 b13 b12 b11 b10 b9
(2)
(1) Data section
(2) Sign bit 0: Positive, 1: Negative
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
CH Digital output value
CH Digital output value (in FX3 allocation
mode function)
Description
Enable
Disable
CH1
304
133
CH1
305
4160
b8 b7 b6 b5 b4 b3 b2
(1)
CH1
400
1000
CH2 CH3
CH2 CH3
b1 b0
CH2 CH3
600 800
1002 1004
CH4
CH4
CH4
1000
1006
APPX
Appendix 4 Buffer Memory Areas
A
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