Display Memory Interface Timing; Write Data To Display Memory; Table 7-10: Write Data To Display Memory; Figure 20: Write Data To Display Memory - Epson SED1352 Technical Manual

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7.3 Display Memory Interface Timing

7.3.1 Write Data to Display Memory

VA[15:0]
VSC0#, VSC1#
VWE#
VOE#
Hi-Z
VD[15:0]
Symbol
t1
Address cycle time
VA[15:0], VCS0# and VCS1# valid before
t2
VWE# falling edge
VA[15:0], VCS0# and VCS1# hold from
t3
VWE# rising edge
t4
Pulse width of VWE#
t5
VD[15:0] setup to VWE# rising edge
t6
VD[15:0] hold from VWE# rising edge
Where MCLK period = 1/f
Hardware Functional Specification
Issue Date: 99/07/28
VALID
t1
t2
t4
Hi-Z
INPUT

Figure 20: Write Data to Display Memory

Table 7-10: Write Data to Display Memory

Parameter
, or 2/f , or 4/f depending on which mode the chip is in. (see section 9.2 and 9.3).
OSC OSC OSC
t3
t6
t5
Hi-Z
OUTPUT
3V/3.3V
Min Typ Max
MCLK - 10
MCLK/2 -
20
0
MCLK/2 - 5
MCLK/2 -
20
0
Page 37
Hi-Z
INPUT
5V
Min Typ Max Units
MCLK -
10
MCLK/2 -
10
0
MCLK/2 -
5
MCLK/2 -
20
0
SED1352
X16-SP-001-16
ns
ns
ns
ns
ns
ns