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Pulse-Width Modulator for Motor Control (PWMMC)
12.3.2 Prescaler
To permit lower PWM frequencies, a prescaler is provided which will divide the PWM clock frequency by
1, 2, 4, or 8.
Table 12-1
clock frequency. This prescaler is buffered and will not be used by the PWM generator until the LDOK bit
is set and a new PWM reload cycle begins.
12.4 PWM Generators
Pulse-width modulator (PWM) generators are discussed in this subsection.
12.4.1 Load Operation
To help avoid erroneous pulse widths and PWM periods, the modulus, prescaler, and PWM value
registers are buffered. New PWM values, counter modulus values, and prescalers can be loaded from
their buffers into the PWM module every one, two, four, or eight PWM cycles. LDFQ1 and LDFQ0 in PWM
control register 2 are used to control this reload frequency, as shown in
arrives, regardless of whether an actual reload occurs (as determined by the LDOK bit), the PWM reload
flag bit in PWM control register 1 will be set. If the PWMINT bit in PWM control register 1 is set, a CPU
interrupt request will be generated when PWMF is set. Software can use this interrupt to calculate new
PWM parameters in real time for the PWM module.
122
shows how setting the prescaler bits in PWM control register 2 affects the PWM
Table 12-1. PWM Prescaler
Prescaler Bits
PRSC1 and PRSC0
00
01
10
11
Table 12-2. PWM Reload Frequency
Reload Frequency Bits
LDFQ1 and LDFQ0
00
01
10
11
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
PWM Clock Frequency
f
OP
f
/2
OP
f
/4
OP
f
/8
OP
Table
PWM Reload Frequency
Every PWM cycle
Every 2 PWM cycles
Every 4 PWM cycles
Every 8 PWM cycles
12-2. When a reload cycle
Freescale Semiconductor
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