Instruction Timing Tables - Motorola CPU32 Reference Manual

8.3 Instruction Timing Tables

The following assumptions apply to the times shown in the tables in this section:
• A 16-bit data bus is used for all memory accesses.
• Memory access times are based on two clock bus cycles with no wait states.
• The instruction pipeline is full at the beginning of the instruction and is refilled
by the end of the instruction.
Three values are listed for each instruction and addressing mode:
Head The number of cycles available at the beginning of an instruction to com-
plete a previous instruction write or to perform a prefetch.
Tail The number of cycles an instruction uses to complete a write.
Cycles Four numbers per entry, three contained in parentheses.
The outer number is the minimum number of cycles required for the in-
struction to complete.
Numbers within the parentheses represent the number of bus accesses
performed by the instruction.
The first number is the number of operand read accesses performed by
the instruction.
The second number is the number of instruction fetches performed by
the instruction, including all prefetches that keep the instruction and the
instruction pipeline filled.
The third number is the number of write accesses performed by the in-
struction.
As an example, consider an ADD.L (12, A3, D7.W ∗ 4), D2 instruction.
Section 8.3.5 Arithmetic/Logic Instructions shows that the instruction has a head =
0, a tail = 0, and cycles = 2 (0/1/0). However, in indexed, address register Indirect ad-
dressing mode, additional time is required to fetch the effective address.
Section 8.3.1 Fetch Effective Address gives addressing mode data. For (d
Xn.Sz ∗ Scale), head = 4, tail = 2, cycles = 8 (2/1/0). Because this example is for a long
access and the FEA table lists data for word accesses, add two clocks to the tail and
to the number of cycles ("X" table notation), to obtain head = 4, tail = 4, cycles = 10 (2/
1/0).
Assuming that no trailing write exists from the previous instruction, effective address
calculation requires six clocks. Replacement fetch for the effective address occurs
during these six clocks, leaving a head of four. If there is no time in the head to perform
a prefetch, due to a previous trailing write, then additional time to do the prefetches
must be allotted in the middle of the instruction or after the tail.
MOTOROLA
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INSTRUCTION EXECUTION TIMING
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CPU32
REFERENCE MANUAL