Specifications
Note
PWM Outputs (CIO 101.00 and CIO 101.01)
2-2-4
Built-in Analog I/O Specifications (XA CPU Units Only)
Analog I/O Terminal Block Arrangement
Note
(1) The load for the above values is assumed to be the resistance load, and
does not take into account the impedance for the connecting cable to the
load.
(2) Due to distortions in pulse waveforms resulting from connecting cable im-
pedance, the pulse widths in actual operation may be smaller than the
values shown above.
Item
Max. switching capacity
Max. output frequency
PWM output accuracy
Output waveform
1
2
3
4
5
6
A/D
9 10 11 12 13 14 15 16
D/A
Pin
Function
1
IN1+
2
IN1−
3
IN2+
4
IN2−
5
IN3+
6
IN3−
7
IN4+
8
IN4−
Do not connect the shield.
Specification
30 mA/4.75 to 26.4 VDC
1 kHz
For ON duty +5%, −0%/1 kHz output.
OFF
ON
t
ON
T
7
8
Pin
Function
9
OUT V1+
10
OUT I1+
11
OUT 1−
12
OUT V2+
13
OUT I2+
14
OUT 2−
15
IN AG*
16
IN AG*
Section 2-2
t
ON
× 100%
ON duty =
T
61