Omron CP1H CPU Operation Manual page 248

Cp1h cpu unit

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High-speed Counters

Software Reset

sequently, when the Reset Bit is turned ON in the ladder program, the phase-

Z signal does not become effective until the next PLC cycle.

The high-speed counter's PV is reset when the corresponding High-speed

Counter Reset Bit goes from OFF to ON.

The CPU Unit recognizes the OFF-to-ON transition of the High-speed

Counter Reset Bit only at the beginning of the PLC cycle during the oversee-

ing processes. Reset processing is performed at the same time. The OFF-to-

ON transition will not be recognized if the Reset Bit goes OFF again within the

(1) The comparison operation can be set to stop or continue when a high-

speed counter is reset. This enables applications where the comparison op-

eration can be restarted from a counter PV of 0 when the counter is reset.

(2) When using analog input/output (XA type only) or pulse output 2/3, pay

attention to the possibility that it may take up to 100µs to reset the existing

value of the high-speed counter due to Z-phase signal (reset input) of the

high-speed counter 3.

(3) When the counter mode is set to incremental pulse and numeric range

mode to ring mode, pay attention to the possibility that it may take time to

reset the existing value of the high-speed counter due to Z-phase signal

(reset input).

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