Omron CP1H CPU Operation Manual page 247

High-speed Counters
Circular (Ring) Mode
Reset Methods
Phase-Z Signal + Software
Reset
Lower and Upper Limits of the Range
The following diagrams show the lower limit and upper limit values for incre-
ment mode and up/down mode.
Increment Mode
0
(000000 hex)
Up/Down Mode
−2147483648
(80000000 hex)
PV underflow
Input pulses are counted in a loop within the set range. The loop operates as
follows:
• If the count is incremented from the max. ring count, the count will be
reset to 0 automatically and incrementing will continue.
• If the count is decremented from 0, the count will be set to the max. ring
count automatically and decrementing will continue.
Consequently, underflows and overflows cannot occur when ring mode is
used.
Count value
32 −1
2
Max. ring
count
0
Max. Ring Count
Use the PLC Setup to set the max. ring count (Circular Max. Count), which is
the max. value of the input pulse counting range. The max. ring count can be
set to any value between 00000001 and FFFFFFFF hex.
Restrictions
• There are no negative values in ring mode.
• If the max. ring count is set to 0 in the PLC Setup, the counter will operate
with a max. ring count of FFFFFFFF hex.
The high-speed counter's PV is reset when the phase-Z signal (reset input)
goes from OFF to ON while the corresponding High-speed Counter Reset Bit
is ON.
The CPU Unit recognizes the ON status of the High-speed Counter Reset Bit
only at the beginning of the PLC cycle during the overseeing processes. Con-
0
(00000000 hex)
Section 5-2
4294967295
(FFFFFFFF hex)
PV overflow
+2147483647
(7FFFFFFF hex)
PV overflow
213