Avaya Media Processing Server 1000 Hardware Installation And Maintenance page 186

Operation and Administration
3. Check for conflicts in IP or MAC address
4. Check if hardware is supported in cardtypes.cfg file
NIC Redundancy
A chassis can be equipped with redundant NIC pair to provide fault tolerance. This pairing requires
that one NIC act as a master while the other is a slave. A slave to master transition can be initiated
by either a software command to the master or, if the slave senses that the master is no longer
available, either a reboot or removal from the backplane.
System clocking is not controlled by the NIC master or slave. System clocks are distributed solely
on the physical location of a card regardless of the mode of a card (master or slave). Reference
clock A is distributed by the NIC in slot 7, and reference clock B is distributed by the NIC in slot 8.
From the tms.cfg file, a chassis that is selected as a reference source requires that the appropriate
NIC receive the clock from the backplane and drive that clock to an external BNC connector. Any
chassis that does not source a clock receives the clock from the external BNC and delivers it to the
backplane.
If a fault occurs in the control logic of a NIC both NICs can enter the same mode, either master or
slave. If this arbitration fails, both cards can become master or slave. In either scenario, the Ethernet
connectivity to the chassis is affected.
If either NIC fails in a chassis, a clock source can be unavailable in that backplane. If a failed NIC
drove one of the reference clocks, then all sink chassis loose the reference clock.
Troubleshooting
1. Verify the configuration files for NICs including tms.cfg and bootptab.
2. Use the serial console to isolate a booting issue.
3. Use arbitration LEDs on NICs to isolate a communication problem between NIC hardware.
PLL
To maintain synchronization between the network spans and the TMS, either the internal PCM
highways and ATM packet a pair of redundant clocks, or timing references are available. System
clock or timing configuration is site-specific and must be defined in the tms.cfg file. The two clock
sources are labeled reference clock A (RefA) and reference clock B (RefB). Both clock sources
must be phase matched. If not, there can be issues with the audio quality of bridged lines. Each
chassis selects which of these two clock sources is a primary reference for the PLL. The other
defaults as a secondary source.
For clock configuration, the NIC receives PLL configuration parameters from the NCD process (that
is, the NCD translates the PLL configuration from the tms.cfg and generates the appropriate NIC
commands). The NIC uses the PLL configuration to determine if the chassis is either a clock source
or a sink.
As a clock or timing source, the NIC issues commands to the appropriate commands to the TMS in
its chassis to select a TMS span as a timing reference. A TMS selected as a timing source derives a
reference from a span and drives an 8 KHz clock onto the common backplane. The NIC receives
the clock, and as a source chassis, drives the clock to the external BNC connectors on the chassis.
A chassis that is not a clocking source is obviously a clock sink. The function of the NIC in this
chassis is to monitor clock signals presented at the external BNC. After the clock becomes
available, it drives that clock onto the backplane therefore making it available to all NIC and TMS
hardware in the chassis.
Avaya Media Processing Server 1000 Hardware Installation and Maintenance
186
Comments? infodev@avaya.com
October 2014