Gtx Rx Latency - Xilinx Virtex-6 FPGA User Manual

GTX RX Latency

Figure C-3
for more details on the GTX RX blocks.
X-Ref Target - Figure C-3
From TX Parallel Data
PLL
RX
DFE
EQ
RX
SIPO
1
Driver
RX OOB
2
3
RX Serial Clock
Table C-2
of the receiver section of the GTX transceiver. The values in the Block Number column
correspond to the circled numbers in
Table C-2: GTX RX Latency
Block Block
Number Name
FPGA RX
9
Interface
PMA +
1+2+3+4
Interface
Comma
5
Detect
8B/10B
6
Decoder
RX Elastic
7
Buffer
Total RX Latency
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
shows a detailed block diagram of the GTX RX. Refer to
To TX Parallel Data
(Near-End PCS (Far-End PMA
Loopback) Loopback)
Comma
Detect
Polarity and
Align
4
5
PRBS
Checker
PMA Parallel Clock (XCLK)
Figure C-3: GTX RX Block Diagram
defines the latency for the specific functional blocks or group of functional blocks
RX_DATA_WIDTH = 8/10
1.5 cycle
RXCOMMADETUSE = 0
1 cycle
RXDEC8B10BUSE = 0
0 cycles
RX_BUFFER_USE = FALSE
0 cycles
Minimum
6.5 cycles
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RX PIPE
Control
RX Status
Control
8B/10B
RX
Decoder
Elastic
6
Buffer
7
Figure C-3.
RX Latency (RXUSRCLK)
RX_DATA_WIDTH = 16/20
2 cycles
4 cycles ± 1 UI
RXCOMMADETUSE = 1
SHOW_REALIGN_COMMA
= TRUE
2.5 to 3.5 cycles
RX_BUFFER_USE = TRUE
(CLK_COR_MIN_LAT/2)
14 + (CLK_COR_MIN_LAT/2) ± 1 UI cycles
GTX RX Latency
RX Overview, page 183
To TX Parallel Data
(Far-End PCS
Loopback)
FPGA RX
Interface
RX
Gear
Box
8
9
FPGA Parallel
PCS Parallel Clock
Clock
(RXUSRCLK)
(RXUSRCLK2)
UG366_aC_03_011111
RX_DATA_WIDTH = 32/40
3 cycles
SHOW_REALIGN_COMMA
= FALSE
2 to 3 cycles
RXDEC8B10BUSE = 1
1 cycle
1.5 to 2.5 cycles +
Maximum
317