Xilinx Virtex-6 FPGA User Manual page 141

Table 3-9: Available Transmitter Resets and the Components Reset by Them
Table 3-10
Table 3-10: Recommended Resets for Common Situations
Notes:
1. The recommended reset has the smallest impact on the other components of the GTX transceiver.
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Component
TX Driver
TX OOB
TX Receiver Detect
TX PMA
for PCIe Designs
TX PLL
PISO
Loopback Loopback Paths
lists the recommended resets for various situations.
Situation
After power up and configuration
After turning on a reference clock
to the TX PLL
After changing the reference clock
to the TX PLL
After assertion/deassertion of
TXPOWERDOWN
TX rate change with the TX buffer
bypassed
TX rate change with TX buffer
enabled
TX parallel clock source reset
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✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
✓ ✓ ✓
Components to be Reset
Entire GTX TX
Entire GTX TX
Entire GTX TX
Entire GTX TX
TX PCS, TX Phase Alignment
TX PLL Output Clock Dividers,
TX PCS
TX PLL Output Clock Dividers,
TX Delay Aligner, TX Phase
Alignment, TX PCS
TX Initialization
✓
Recommended
(1)
Reset
After configuration,
GTX TX is reset
automatically
GTXTXRESET
GTXTXRESET
GTXTXRESET
GTXTEST[1],
TXRESET
GTXTEST[1],
TXRESET
GTXTEST[1],
TXDLYALIGNRESET,
TXRESET
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