Xilinx Virtex-6 FPGA User Manual page 6

Date Version
05/24/10 2.3
10/01/10 2.4
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
Added description of buffer bypass mode to
Added Power-Down Requirements for TX and RX Buffer
Added description of TX buffer bypass to
Description, page 155.
Added description of RX buffer bypass to
Functional Description, page 261
GTXTEST[12:0] from Table
Updated Managing Unused GTX
Analog Power Supply Pins, and
and Table 5-4. Added note about buffer bypass mode to
Reference Clock Toggling.
Updated Functional Description,
and GTX TX Reset in Response to GTXTXRESET
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Revision
Multiple External Reference Clocks Use
Functional Description, page 136
Functional Description, page
with description of buffer bypass mode. Removed
4-52.
Transceivers. Replaced "group" with "bank" in
Partially Unused Quad
GTX TX Reset in Response to Completion of
Pulse.
Bypass.
and Functional
231. Updated
Table
Column. Added Note 2 to
Reference Clock Checklist. Added
Configuration,
UG366 (v2.5) January 17, 2011
Model.
5-1,
Table 5-3