Xilinx Virtex-6 FPGA User Manual page 157

Table 3-19
Table 3-19: TX Buffer Bypass Attributes
Attribute
POWER_SAVE
TX_BUFFER_USE
TX_BYTECLK_CFG[5:0]
TX_DATA_WIDTH
TX_DLYALIGN_CTRINC
TX_DLYALIGN_LPFINC
TX_DLYALIGN_MONSEL
TX_DLYALIGN_OVRDSETTING
TX_PMADATA_OPT
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
defines the TX buffer bypass attributes.
Type
10-bit POWER_SAVE[4]:
Binary
Mux select for the TXOUTCLK output clock. Must be tied to 1'b1.
1'b0: Use the TX Delay Aligner
1'b1: Bypass the TX Delay Aligner
POWER_SAVE[5]:
Mux select for the RXRECCLK output clock. Must be tied to 1'b1 when
RX buffer is used (RX_BUFFER_USE = TRUE). When RX buffer is
bypassed, refer to
Buffer, page 235.
1'b0: Use the RX Delay Aligner
1'b1: Bypass the RX Delay Aligner
All other bits are reserved. Use recommended values from the Virtex-
6 FPGA GTX Transceiver Wizard.
Boolean Use or bypass the TX buffer.
TRUE: Use the TX buffer (normal mode).
FALSE: Bypass the TX buffer (advanced feature).
6-bit Hex Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Transceiver Wizard.
Integer Sets the transmitter external data width
8/10: 1-byte interface
16/20: 2-byte interface
32/40: 4-byte interface
If 8B10B is used, this attribute must be a multiple of 10.
4-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Binary Transceiver Wizard.
4-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Binary Transceiver Wizard.
3-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Binary Transceiver Wizard.
8-bit Sets the overdrive value for the TX delay aligner. This attribute takes
Binary effect when TXDLYALIGNOVERRIDE is driven High.
1-bit This attribute controls the inverter that optimizes the clock path within
Binary the GTX transceiver for different mode of operations. The attribute
must be set as follows:
0: Use when TX_BUFFER_USE = TRUE
1: Use when TX_BUFFER_USE = FALSE
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Description
Using the RX Phase Alignment Circuit to Bypass the
TX Buffer Bypass
157